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參數(shù)資料
| 型號(hào)： | A42MX16-3TQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 97/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3TQ100 |
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78
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 4 - T0PR: Timer0 Prescaler Reset Bit
Writing T0PR to one restarts the Timer0 Watchdog Prescaler. If T0PR is written to one, hard-
ware will clear this bit after four clock cycles. Only if the watchdog function is disabled the Timer0
Watchdog Prescaler can be restarted. Additionally, the T0PR bit should only be set to one if the
motion sensor functionality is disabled via bit SMEN located in the SCR register. Otherwise, a
malfunction could occur in the motion sensor circuitry caused by an asynchronous reset of
Timer0.
Bit 3 - T0IE: Timer0 Interrupt Enable Bit
Writing T0IE to one enables a interval timer interrupt if the I bit in SREG is set. Writing T0IE to
zero disables the interrupt. The corresponding Interrupt Vector is executed when the T0F Flag,
located in T10IFR, is set.
Bits 2..0 - T0PAS2..0: Timer0 Prescaler A Select Bits 2 - 0
The T0PAS2, T0PSA1, and T0PAS0 bits determine the Timer0 prescaling clock output (CLK
T0).
The different prescaling values and their corresponding time-out periods are shown in Table
3.13.3.3
Timer1/0 Interrupt Flag Register – T10IFR
Bits 7..2 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 1 - T1F: Timer1 Flag Bit
When the interval timer in Timer1 generates an output clock pulse (CLK
T1) the T1F bit is set
(one). If the I-bit in SREG and the T1IE bit is set (one) at T1CR the MCU will jump to the corre-
sponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
Table 3-33.
Timer0 Prescaler A Select Bit Description
T0PAS2 T0PAS1 T0PAS0
Number of Oscillator Cycles
(SCL)
Typical Time-out at VCC = 3V/25°C
and T
SCL ≈
1 / 90kHz for CLK
T0
0
8cycles
89s
0
1
32cycles
350s
0
1
0
128cycles
1.4ms
0
1
1K cycles
11.4ms
1
0
4K cycles
45.5ms
1
0
1
32K cycles
365ms
1
0
256K cycles
2.9s
1
1024K cycles
11.65s
Bit
7
654
321
0
-
T1F
T0F
T10IFR
Read/Write
RR
RRR
R
R/W
Initial Value
0
000
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-3TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-3TQ100 | 40MX and 42MX FPGA Families |
| A42MX02-3TQ100A | 40MX and 42MX FPGA Families |
| A42MX04-3TQ100A | 40MX and 42MX FPGA Families |
| A42MX09-3TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3TQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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