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參數(shù)資料
| 型號： | A42MX16-3TQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 80/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3TQ100 |
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62
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
MOSI/PCINT3 - Port B, Bit 3
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB3. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB3 bit.
PCINT3, Pin Change Interrupt Source 3: The PB3 pin can serve as an external interrupt source.
T2I/PCINT2 - Port B, Bit 2
T2I: External input clock for Timer1, Timer2 or Timer3. The pin has to be configured as an input
(DDB2 set (zero)) to serve this function.
PCINT2, Pin Change Interrupt Source 2: The PB2 pin can serve as an external interrupt source.
T3O/PCINT1 - Port B, Bit 1
T3O, Timer3 modulator output: The PB1 pin can serve as an external output for the
Timer/Counter3 modulator. The pin has to be configured as an output (DDB1 set (one)) to serve
this function.
PCINT1, Pin Change Interrupt Source 1: The PB1 pin can serve as an external interrupt source.
T3ICP/PCINT0 - Port B, Bit 0
T3ICP - Timer3 Input Capture pin: The PB0 pin can act as an external Input Capture pin for
Timer/Counter3. The pin has to be configured as an input (DDB0 set (zero)) to serve this
function.
PCINT0, Pin Change Interrupt Source 0: The PB0 pin can serve as an external interrupt source.
Table 3-23 and Table 3-29 relate the alternate functions of Port B to the overriding signals
shown in Table 3-21 on page 60. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 3-23.
Over Alternate Functions in PB7..PB4
Signal Name
PB7/SS/PCINT7
PB6/PCINT6
PB5/SCK/PCINT5
PB4/MISO/PCINT4
PUOE
SPE
× NMSTR
0
SPE
× NMSTR
SPE
× MSTR
PUOV
PORTB7
× NPUD
0
PORTB5
× NPUD
PORTB4
× NPUD
DDOE
SPE
× NMSTR
0
SPE
× NMSTR
SPE
× MSTR
DDOV
0
PVOE
0
SPE
× MSTR
SPE
× NMSTR
PVOV
0
SCK OUTPUT
SPI SLAVE OUTPUT
DIEOE
PCINT7
× PCIE0
PCINT6
× PCIE0
PCINT5
× PCIE0
PCINT4
× PCIE0
DIEOV
1
DI
PCINT7 INPUT
SPI SS
PCINT6 INPUT
PCINT5 INPUT
SCK INPUT
PCINT4 INPUT
SPI MSTR INPUT
AIO
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| A42MX24-3TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-3TQ100 | 40MX and 42MX FPGA Families |
| A42MX02-3TQ100A | 40MX and 42MX FPGA Families |
| A42MX04-3TQ100A | 40MX and 42MX FPGA Families |
| A42MX09-3TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3TQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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