參數(shù)資料
型號： A42MX16-3TQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 63/120頁
文件大?。?/td> 854K
代理商： A42MX16-3TQ100
47
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.10
Interrupts
This section describes the specifics of the interrupt handling as performed in ATA6289. For a
general explanation of the Atmel
AVR interrupt handling, refer to Section 3.5.7 “Reset and
Interrupt Handling” on page 17. At the ATA6289 the Reset Vector is affected by the BOOTRST
fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR register, see
3.10.1
Interrupt Vectors
Table 3-16.
Reset and Interrupt Vectors
Vector No. Program Address(1)
Source
Interrupt Definition
1
0x000(2)
RESET
External pin, power-on reset, brown-out reset,
watchdog reset, and temperature shutdown reset
2
0x001
INT0
External interrupt request 0
3
0x002
INT1
External interrupt request 1
4
0x003
PCINT0
Pin change interrupt request 0
5
0x004
PCINT1
Pin change interrupt request 1
6
0x005
PCINT2
Pin change interrupt request 2
7
0x006
INTVM
Voltage monitoring interrupt
8
0x007
SENINT
Sensor interface interrupt
9
0x008
INTT0
Timer0 interval interrupt
10
0x009
LFWP
LF-receiver wake-up interrupt
11
0x00A
T3CAP
Timer/Counter3 capture event
12
0x00B
T3COMA
Timer/Counter3 compare match A
13
0x00C
T3COMB
Timer/Counter3 compare match B
14
0x00D
T3OVF
Timer/Counter3 overflow
15
0x00E
T2CAP
Timer/Counter2 capture event
16
0x00F
T2COM
Timer/Counter2 compare match
17
0x010
T2OVF
Timer/Counter2 overflow
18
0x011
SPISTC
SPI serial transfer complete
19
0x012
LFRXB
LF-receiver receive buffer interrupt
20
0x013
INTT1
Timer1 interval interrupt
21
0x014
T2RXB
Timer2 SSI receive buffer interrupt
22
0x015
T2TXB
Timer2 SSI transmit buffer interrupt
23
0x016
T2TXC
Timer2 SSI transmit complete interrupt
24
0x017
LFREOB
LF-receiver end of burst interrupt
25
0x018
EXCM
External input clock break down interrupt
26
0x019
EEREADY
EE ready interrupt
27
0x01A
SPM READY Store program memory ready
Notes:
1. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot
flash section. The address of each interrupt vector will then be the address in this table added
to the start address of the boot flash section.
2. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at
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A42MX16-3TQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3TQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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