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參數(shù)資料
| 型號(hào)： | A42MX16-3TQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 23/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3TQ100 |
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119
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-56. Sensor Interface Block
For further information on the resolution of the three different units MSIU, CSIU and VSIU see
3.15.1
Motion Sensor Interface Unit (MSIU)
This section describes how a measurement with a Motion Sensor at Pin S2 is executed and how
a motion weak-up can be generated.
To enable the MSIU, SMEN bit in the SCR register must be set (one). The MSIU needs the
Timer0 clock (CLK
SEN) for starting the motion measurements (starting the state machine) period-
ically, i.e.Timer0 has to be activated and TOBS[2..0] bits in the T0CR register must be set so
that CLKSEN is directed to the Motion Sensor Interface, see also Section 3.13.3 “Timer0 with
Watchdog/Interval Timer” on page 73ff. Before changing the T0CR register MSIU needs to be
disabled. After T0CR register is set the motion sensor interface can be enabled again. In that
way a safe restart of the state machine of MSIU is guaranteed.
The capacitance of the external Motion sensor C
M (at pin S2) forms together with the internal
capacitance C
Ref a capacitive voltage divider, see Figure 3-57 on page 120. If switch Sw1 is
closed, controlled by the state machine, a voltage V
SEN will be generated which is a function of
C
M.
V
CC is the supply voltage of the ATA6289.
If the application starts to rotate the capacitance of the motion/acceleration sensor will increase,
meanwhile the sensor voltage V
SEN decreases. A low offset auto zero comparator stage com-
pares the sensor input voltage on pin S2 with the internal calibrated reference voltage (V
Ref). If
the sensor voltage on pin S2 is lower than the internal reference voltage V
Ref, MSENOS signal
gets high and MSENO bit in the SSFR register will be set. With polling the MSENO bit you can
weak up the ATA6289 if this bit is set.
MUX
SMSSEN (1:0)
Control
MSENO
MSENOS
SENO
SENINT
Capacitor Sensor
Interface
Unit
(CSIU)
Voltage Sensor
Interface
Unit
(VSIU)
Motion Sensor
Interface
Unit
(MSIU)
CLKSEN
fV
fC
S1 (CEX1)
S2 (CEX2)
S0 (CEX0)
MSIE
V
SEN
C
Ref
C
Ref
C
M
+
--------------------------
V
CC
×
=
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| A42MX24-3TQ100 | 40MX and 42MX FPGA Families |
| A42MX36-3TQ100 | 40MX and 42MX FPGA Families |
| A42MX02-3TQ100A | 40MX and 42MX FPGA Families |
| A42MX04-3TQ100A | 40MX and 42MX FPGA Families |
| A42MX09-3TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3TQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3TQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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