In-System Programming (ISP) of Actel’s Low-Power Flash Devices Using FlashPro3
v1.1
16- 5
1. In a trusted programming environment, you can program the device using the unencrypted
(plaintext) programming file.
2. You can program the AES Key in a trusted programming environment and finish the final
programming in an untrusted environment using the AES-encrypted (cipher text)
programming file.
3. For the remote ISP updating/reprogramming, the AES Key stored in the device enables the
encrypted programming bitstream to be transmitted through the untrusted network
connection.
Actel low-power flash devices also provide the unique Actel FlashLock feature, which protects the
Pass Key and AES Key. Unless the original FlashLock Pass Key is used to unlock the device, security
settings cannot be modified. Low-power flash devices do not support read-back of FPGA core-
programmed data; however, the FlashROM contents can selectively be read back (or disabled) via
the JTAG port based on the security settings established by the Actel Designer software. Refer to
FlashROM and Programming Files
Each low-power flash device has 1 kbit of on-chip, nonvolatile flash memory that can be accessed
from the FPGA core. This nonvolatile FlashROM is arranged in eight pages of 128 bits
(Figure 16-3).Each page can be programmed independently, with or without the 128-bit AES encryption. The
FlashROM can only be programmed via the IEEE 1532 JTAG port and cannot be programmed from
the FPGA core. In addition, during programming of the FlashROM, the FPGA core is powered down
automatically by the on-chip programming control logic.
Using FlashROM combined with AES, many subscription-based applications or device serialization
applications are possible. SmartGen supports easy management of the FlashROM contents even
over large numbers of devices. SmartGen can support FlashROM contents that contain the
following:
Static values
Figure 16-2 Different ISP Use Models
Source
Plain Text
AES
Encryption
Source
Encrypted Bitstream
TCP/IP
FlashROM
AES
Decryption
FPGA
Core
IGLOO or ProASIC3 Device
Option
1
Option
2
Option
3