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參數(shù)資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 45/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
5 of 84
The PNX8510/11 supports color space conversion only in the primary RGB standard definition
data path. For the high definition part of the primary video data path and for the secondary video
data path no color space conversion is available. Hence the video data has to be provided in the
display destination color space.
Aside from built-in video encoders, which generate all necessary timing and filtering for an
appropriate sync raster for PAL, NTSC and SECAM, the PNX8510/11 contains a separate
raster-generation engine which also supports but is not limited to the HD-formats, such as the
SMPTE 274M. Furthermore the PNX8510/11 contains an up-sampling filter to convert 4:2:2
formats (other than standard definition formats) to 4:4:4.
Note: In the case of combined double D1 mode, no secondary display channel is available.
If the interface is operated in D1 mode, the data stream presented to the interface has to be D1
compliant i.e., the maximum and minimum codes (8-bit 0x00 0xFF, 10-bit 0x000 0x3FF) must
not occur during active video.
A detailed description of video input data formats can be found in Section 2.2 Video Input
Modes. The video modes mentioned in Section 2.2 correspond to the settings of the
DEMUX_MODE bits in the register 0x95 VMUXCTL. If the video interface clock frequency is not
equivalent to the processing and the video DAC operation frequency the appropriate divider
registers in the audio/clock register section have to be programmed. As a general rule the
following settings should be used:
422 YUV SD Single Interface Mode
27MHz interface clock
27MHz processing clock
27MHz DAC clock
444RGB 2FH Single Interface Mode
81MHz interface clock
27MHz processing clock
27MHz DAC clock
422 YUV 1080i Double Interface Mode
74.25MHz interface clock
74.25MHz processing clock
74.25MHz DAC clock
2.2 Video Input Modes
The PNX8510/11 video interface supports a wide variety of video formats. The video interface is
designed in a generic fashion. It is de-coupled from the actual video data paths in the system
and imposes only a few restrictions on the video data streams provided to the chip.
This section explains the possible video stream formats and provides details on synchronizing
the PNX8510/11 with respect to a particular video data format.
The PNX8510/11 accepts the following video formats on a single interface with up to 81 MHz
interface clock:
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