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參數(shù)資料
| 型號： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 20/84頁 |
| 文件大小： | 1054K |
| 代理商： | 935269580557 |
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Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
27 of 84
6.
Clock Module
All of the PNX8510/11 modules receive their input clocks from the clocks module. The top level
structure of the clocks module is shown below.
The PNX8510/11 in normal operation mode receives four external clocks. Two clocks dv_clk1
and dv_clk2 are the clocks used for the primary and secondary video data paths. The other two
clocks assemble the audio over-sampling clocks for the primary and secondary audio channel.
The PNX8510/11 video clocks are used to create two internal clocks: one for operating the video
input interface (clk_dv1_if, clk_dv2_if), and one for operating the main video processing pipeline
(clk_dv1_proc, clk_dv2_proc).
The audio interface normally operates in slave mode (over-sampling clock, word select and bit
clock are provided from the externally connected I2S master). However the PNX8510/11 can be
operated in master mode. This mode only requires the over-sampling clock to be provided. The
bit clock and the word select signals are subdivided from the over-sampling clock and provided
to the chip pins.
Figure 21: Clocks Module
I2C decoder module
clocks_video_sub_1
clocks_audio_sub_2
clocks_audio_sub_1
clocks_video_sub_2
dv_clk1
dv_clk2
i2s_aos1_clk
i2s_aos2_clk
clk_dv1_if
clk_dv1_proc
clk_dv2_if
clk_dv2_proc
sclk_a1
ws_a1
sclk_a2
ws_a2
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