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參數(shù)資料
| 型號(hào)： | 935269580557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, HTQFP-100 |
| 文件頁(yè)數(shù)： | 16/84頁(yè) |
| 文件大?。?/td> | 1054K |
| 代理商： | 935269580557 |
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Philips Semiconductors
PNX8510/11
Analog Companion Chip
9397 750 08865
Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved.
Product data
Rev. 02 — 8 October 2001
23 of 84
3.1.1 Audio Input Timing
The following timing diagrams illustrate the different modes of operation for the I2S interface
used in the PNX8510/11.
3.2 Mute Modes
The audio modules of the PNX8510/11 have several mute functions. The mute operation is
controlled via the programming registers quickmute, and mutemode.
Quick Mute: This is an overriding quickmute on the master channel, which mutes the
interpolator output signal in 32 samples using the cosine roll-off coefficients. This means
whenever the quickmute register is set to one, independent of what the mute setting of the
microcontroller is, the output is muted.
Figure 17: Input Formats. Justification bit is not delayed.
MSB
LSB
WS
SCK
SD
MSB
LSB
1) MSB first / MSB justified format (MSB):
MSB
LSB
WS
MSB
LSB
2) MSB first / LSB justified format (Japanese I2S 16, 18, 20, 24 bit):
: position fixed.
: position may vary with wordsize.
Figure 18: Input Format. Justification bit is one bit clock delayed.
MSB
LSB
WS
SCK
SD
MSB
LSB
1) MSB first / MSB justified format (Philips I2S):
: position fixed.
: position may vary with wordsize.
Table 13: I2S Signals
Port
Description
SCK
Bit clock
SD
PCM data
WS
Word Select; left right clock is equal to the sample rate.
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