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參數資料
| 型號： | 935268282151 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數： | 8/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282151 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
16
FIELD
DESCRIPTION
TYPE
SIZE
LCtrl
1
Rd/Wr
Link-active status control. This bit is used to control the active status of the LLC as indicated during
self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the
self-ID packet. The LLC is considered active only if both the LPS input is active the and LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the
LPS input.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state
of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active,
then received packets and status information will continue to be presented on the interface, and any
requests indicated on the LREQ input will be processed, even if the LCtrl bit is cleared to 0.
C
1
Rd/Wr
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the “c” field (bit 20) of the self-ID packet. This bit is set to the state
specified by the C/LKON input terminal by a hardware reset and is unaffected by a bus reset.
Jitter
3
Rd
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest
repeater data delay, expressed as (Jitter + 1)
× 20 ns. For the PDI1394P23, this field is 0.
Pwr_Class
3
Rd/Wr
Node power class. This field indicates this node’s power consumption and source characteristics and is
replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state specified by
the PC0–PC2 input terminals upon hardware reset, and is unaffected by a bus reset. See Table 21.
RPIE
1
Rd/Wr
Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set
whenever resume operations begin on any port. This bit is reset to 0 by hardware reset and is
unaffected by bus reset.
ISBR
1
Rd/Wr
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3
s)
arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset.
NOTE: Legacy IEEE Std 1394–1995 compliant PHYs are not capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long
bus reset being performed.
CTOI
1
Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during
tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware
reset, or by writing a 1 to this register bit.
NOTE: If the network is configured in a loop, only those nodes which are part of the loop should
generate a configuration time out interrupt. All other nodes should instead time out waiting for the
tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset.
CPSI
1
Rd/Wr
Cable-power-status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low
indicating that cable power may be too low for reliable operation. This bit is set to 1 by hardware reset,
and set to 0 by writing a 1 to this register bit.
STOI
1
Rd/Wr
State time-out interrupt. This bit indicates that a state time-out has occurred. This bit is reset to 0 by
hardware reset, or by writing a 1 to this register bit.
PEI
1
Rd/Wr
Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for
any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt
enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is
reset to 0 by hardware reset, or by writing a 1 to this register bit.
EAA
1
Rd/Wr
Enable arbitration acceleration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in P1394a (ACK-accelerated arbitration, asynchronous fly-by concatenation,
and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus
reset.
NOTE: The EAA bit should be set only if the attached LLC is P1394a compliant. If the LLC is not
P1394a compliant, use of the arbitration acceleration enhancements can interfere with isochronous
traffic by excessively delaying the transmission of cycle-start packets.
EMC
1
Rd/Wr
Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware
reset and is unaffected by bus reset.
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy
IEEE Std 1394–1995 PHYs. However, use of multispeed concatenation requires that the attached LLC
be P1394a compliant.
Page_Select
3
Rd/Wr
Page_Select. This field selects the register page to use when accessing register addresses 8 through
15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset.
Port_Select
4
Rd/Wr
Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the
port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset
to 0 by hardware reset and is unaffected by bus reset.
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