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參數(shù)資料
| 型號： | 935268282151 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 29/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282151 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
35
The sequence of events for resetting the PHY-LLC interface when it
is in the nondifferentiated mode of operation (ISO terminal is high) is
as follows:
1. Normal operation. Interface is operating normally, with LPS
asserted, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line. In the above diagram, the LPS signal is shown
as a non-pulsed level signal. However, it is permissible to use a
pulsed signal for LPS in a direct connection between the PHY
and LLC; a pulsed signal is required when using an isolation
barrier (whether of the Philips Bus Holder type or Annex J type).
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives
its LREQ output low.
3. Interface reset. After TLPS_RESET time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and drives
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
4. Interface restored. After the minimum TRESTORE time, the LLC
may again assert LPS active. (The minimum TRESTORE interval
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described below.
If the LLC continues to keep the LPS signal deasserted, it requests
that the interface be disabled. The PHY disables the interface when
it observes that LPS has been deasserted for TLPS_DISABLE. When
the interface is disabled, the PHY sets its CTL and D outputs as
stated above for interface reset, but also stops SYSCLK activity. The
interface is also placed into the disabled condition upon a hardware
reset of the PHY. The timing for interface disable is shown in
Figure 22 and Figure 23.
When the interface is disabled, the PHY will enter a low-power state
if none of its ports is active.
TLPS_RESET
TLPS_DISABLE
ISO
SYSCLK
CTL0, CTL1
D0 – D7
LREQ
LPS
(low)
(a)
(c)
(b)
TLPSL
TLPSH
SV01812
(d)
Figure 22.
Interface Disable, ISO Low
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