參數(shù)資料
型號(hào)： 935268282151
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 20/42頁(yè)
文件大?。?/td> 218K
代理商： 935268282151
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
27
SV01758
LR0
LR1
LR2
LR3
LR(n–2)
LR(n–1)
Figure 14.
LREQ Request Stream
18.1
LLC service request
To request access to the bus, to read or write a PHY register, or to
control arbitration acceleration, the LLC sends a serial bit stream on
the LREQ terminal as shown in Figure 14.
The length of the stream will vary depending on the type of request
as shown in Table 11.
Table 11. Request Stream Bit Length
REQUEST TYPE
NUMBER OF BITS
Bus request
7 or 8
Read register request
9
Write register request
17
Acceleration control request
6
Regardless of the type of request, a start bit of 1 is required at the
beginning of the stream, and a stop bit of 0 is required at the end of
the stream. The second through fourth bits of the request stream
indicate the type of the request. In the descriptions below, bit 0 is the
most significant, and is transmitted first in the request bit stream.
The LREQ terminal is normally low.
Encoding for the request type is shown in Table 12.
Table 12. Request Type Encoding
LR1–LR3
NAME
DESCRIPTION
000
ImmReq
Immediate bus request. Upon
detection of idle, the PHY takes
control of the bus immediately
without arbitration
001
IsoReq
Isochronous bus request. Upon
detection of idle, the PHY arbitrates
for the bus without waiting for a
subaction gap.
010
PriReq
Priority bus request. The PHY
arbitrates for the bus after a
subaction gap, ignores the fair
protocol.
011
FairReq
Fair bus request. The PHY
arbitrates for the bus after a
subaction gap, follows the fair
protocol
100
RdReg
The PHY returns the specified
register contents through a status
transfer.
101
WrReg
Write to the specified register.
110
AccelCtl
Enable or disable asynchronous
arbitration acceleration.
111
Reserved
Reserved.
For a bus request the length of the LREQ bit stream is 7 or 8 bits, as
shown in Table 13.
Table 13. Bus Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer
(always 1).
1–3
Request Type
Indicates the type of bus request. See
Table 12.
4–6
Request Speed
Indicates the speed at which the PHY
will send the data for this request. See
Table 14 for the encoding of this field.
7
Stop Bit
Indicates the end of the transfer
(always 0). If bit 6 is 0, this bit may be
omitted.
The 3-bit request speed field used in bus requests is shown in
Table 14.
Table 14. Bus Request Speed Encoding
LR4–LR6
DATA RATE
000
S100
010
S200
100
S400
All others
Invalid
NOTE:
The PDI1394P23 will accept a bus request with an invalid speed
code and process the bus request normally. However, during packet
transmission for such a request, the PDI1394P23 will ignore any
data presented by the LLC and will transmit a null packet.
For a read register request, the length of the LREQ bit stream is
9 bits as shown in Table 15.
Table 15. Read Register Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer
(always 1).
1–3
Request Type
A 100 indicating this is a read register
request.
4–7
Address
Identifies the address of the PHY register
to be read.
8
Stop Bit
Indicates the end of the transfer
(always 0).
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