參數(shù)資料
型號: 935268282118
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 6/42頁
文件大?。?/td> 218K
代理商: 935268282118
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
14
13.0
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
R
ΘjA
Junction-to-free-air thermal resistance
Board mounted, no air flow
68
°C/W
14.0
AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmit jitter
TPA, TPB
0.15
ns
Transmit skew
Between TPA and TPB
0.10
ns
tr
TPA, TPB differential output voltage rise time
10% to 90%; At 1394 connector
0.5
1.2
ns
tf
TPA, TPB differential output voltage fall time
90% to 10%; At 1394 connector
0.5
1.2
ns
tSU
Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK
50% to 50%; See Figure 2
5
ns
tH
Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK
50% to 50%; See Figure 2
0
ns
tD
Delay time SYSCLK to CTL0, CTL1, D0–D7
50% to 50%; See Figure 3
0.5
11
ns
CL
Capacitance load value CTL0, CTL1, D0–D7,
SYSCLK
10
pF
Ci
Input capacitance CTL0, CTL1, D0–D7, LREQ
3.3
pF
15.0
TIMING WAVEFORMS
SV01098
56
TPAn+
TPBn+
TPAn–
TPBn–
Figure 1.
Test load diagram
SV01099
tSU
tH
SYSCLK
Dn, CTLn, LREQ
Figure 2.
Dn, CTLn, LREQ input setup and hold times
SV01803
tD
SYSCLK
Dn, CTLn
Figure 3.
Dn, CTLn, output delay relative to SYSCLK
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