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| 型號： | 935268282118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282118 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
28
For a write register request, the length of the LREQ bit stream is
17 bits as shown in Table 16.
Table 16. Write Register Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer
(always 1).
1–3
Request Type
A 101 indicating that this is a write
register request.
4–7
Address
Identifies the address of the PHY
register to be written to.
8–15
Data
Gives the data that is to be written to the
specified register address.
16
Stop Bit
Indicates the end of the transfer
(always 0).
For an acceleration control request, the length of the LREQ data
stream is 6 bits as shown in Table 17.
Table 17. Acceleration Control Request
BIT(S)
NAME
DESCRIPTION
0
Start Bit
Indicates the beginning of the transfer
(always 1).
1–3
Request Type
A 110 indicating this is an acceleration
control request.
4
Control
Asynchronous period arbitration
acceleration is enabled if 1, and
disabled if 0.
5
Stop Bit
Indicates the end of the transfer
(always 0).
For fair or priority access, the LLC sends the bus request (FairReq or
PriReq) at least one clock after the PHY-LLC interface becomes idle. If
the CTL terminals are asserted to the receive state (10b) by the PHY,
then any pending fair or priority request is lost (cleared). Additionally,
the PHY ignores any fair or priority requests if the Receive state is
asserted while the LLC is sending the request. The LLC may then
reissue the request one clock after the next interface idle.
The cycle master node uses priority bus request (PriReq) to send a
cycle start packet. After receiving or transmitting a cycle start
packet, the LLC can issue an isochronous bus request (IsoReq).
The PHY will clear an isochronous request only when the bus has
been won.
To send an acknowledge packet, the link must issue an immediate
bus request (ImmReq) during the reception of the packet addressed
to it. This is required in order to minimize the idle gap between the
end of the received packet and the start of the transmitted
acknowledge packet. As soon as the receive packet ends, the PHY
immediately grants control of the bus to the LLC. The LLC sends an
acknowledgment to the sender unless the header CRC of the
received packet is corrupted. In this case, the LLC does not transmit
an acknowledge, but instead cancels the transmit operation and
releases the interface immediately; the LLC must not use this grant
to send another type of packet. After the interface is released, the
LLC may proceed with another request.
The LLC may request only one bus request at a time. Once the LLC
issues any request for bus access (ImmReq, IsoReq, FairReq, or
PriReq), it cannot issue another request until the PHY indicates that
the bus request was “l(fā)ost” (bus arbitration lost and another packet
received), or “won” (bus arbitration won and the LLC granted
control). The PHY ignores new bus requests while a previous bus
request is pending. All bus requests are cleared upon a bus reset.
For write register requests, the PHY loads the specified data into the
addressed register as soon as the request transfer is complete. For
read register requests, the PHY returns the contents of the
addressed register to the LLC at the next opportunity through a
status transfer. If a received packet interrupts the status transfer,
then the PHY continues to attempt the transfer of the requested
register until it is successful. A write or read register request may be
made at any time, including while a bus request is pending. Once a
read register request is made, the PHY ignores further read register
requests until the register contents are successfully transferred to
the LLC. A bus reset does not clear a pending read register request.
The PDI1394P23 includes several arbitration acceleration
enhancements which allow the PHY to improve bus performance
and throughput by reducing the number and length of inter-packet
gaps. These enhancements include autonomous (fly-by)
isochronous packet concatenation, autonomous fair and priority
packet concatenation onto acknowledge packets, and accelerated
fair and priority request arbitration following acknowledge packets.
Then enhancements are enabled when the EAA bit in PHY
register 5 is set.
The arbitration acceleration enhancements may interfere with the
ability of the cycle master node to transmit the cycle start packet
under certain circumstances. The acceleration control request is
therefore provided to allow the LLC to temporarily enable or disable
the arbitration acceleration enhancements of the PDI1394P23
during the asynchronous period. The LLC typically disables the
enhancements when its internal cycle counter rolls over indicating
that a cycle start packet is imminent, and then re-enables the
enhancements when it receives a cycle start packet. The
acceleration control request may be made at any time, however, and
is immediately serviced by the PHY. Additionally, a bus reset or
isochronous bus request will cause the enhancements to be
re-enabled, if the EAA bit is set.
18.2
Status transfer
A status transfer is initiated by the PHY when there is status
information to be transferred to the LLC. The PHY waits until the
interface is idle before starting the transfer. The transfer is initiated
by the PHY asserting Status (01b) on the CTL terminals, along with
the first two bits of status information on the D[0:1] terminals. The
PHY maintains CTL = Status for the duration of the status transfer.
The PHY may prematurely end a status transfer by asserting
something other than Status on the CTL terminals. This occurs if a
packet is received before the status transfer completes. The PHY
continues to attempt to complete the transfer until all status
information has been successfully transmitted. There is at least one
idle cycle between consecutive status transfers.
The PHY normally sends just the first four bits of status to the LLC.
These bits are status flags that are needed by the LLC state
machines. The PHY sends an entire 16-bit status packet to the LLC
after a read register request, or when the PHY has pertinent
information to send to the LLC or transaction layers. The only
defined condition where the PHY automatically sends a register to
the LLC is after self-ID, where the PHY sends the physical-ID
register that contains the new node address. All status transfers are
either 4 or 16 bits unless interrupted by a received packet. The
status flags are considered to have been successfully transmitted to
the LLC immediately upon being sent, even if a received packet
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