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參數(shù)資料
| 型號： | 935268282118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282118 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
20
17.0
APPLICATION INFORMATION
390K
PDI1394P23
TPBIAS
CPS
220pF
TPAn+
TPAn–
TPBn+
TPBn–
CABLE
PAIR A
CABLE
PAIR B
CABLE PORT
SV01821
0.3–1.0
F
56
56
56
56
CABLE
5 k
OUTER SHIELD
TERMINATION
POWER PAIR
VP
VG
The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended.
Figure 4.
Twisted pair cable interface connections
OUTER CABLE SHIELD
0.1
F
0.01
F
1 M
CHASSIS GROUND
SV01748
OUTER CABLE SHIELD
CHASSIS GROUND
COMPLIANT DC-ISOLATED
OUTER SHIELD TERMINATION
NON-ISOLATED
OUTER SHIELD TERMINATION
Figure 5.
Cable outer shield termination methods
SV01805
3
6
DGND (AGND)
DVDD (AVDD)
0.1
F
0.001
F
VDD
Use one of these networks per side for all digital power and ground
pins and one per side for all analog power and ground pins. Place
the network as close to the PHY as possible.
Figure 6.
Power supply decoupling network
10 k
SV01806
LPS
LINK POWER
SQUARE WAVE INPUT
10 k
Figure 7.
Non-isolated connection variations for LPS
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