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參數(shù)資料
| 型號： | 935268282118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935268282118 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
34
The sequence of events for resetting the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, and
places its LREQ, CTL, and D outputs into a high-impedance
state (the LLC should terminate any output signal activity such
that signals end in a logic 0 state).
3. Interface reset. After TLPS_RESET time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
4. Interface restored. After the minimum TRESTORE time, the LLC
may again assert LPS active. (The minimum TRESTORE interval
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described on the next page.
TLPS_RESET
TRESTORE
ISO
SYSCLK
CTL0, CTL1
D0 – D7
LREQ
LPS
(high)
(a)
(c)
(d)
(b)
SV01811
Figure 21.
Interface Reset, ISO High
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