
TM1100 Preliminary Data Book
Philips Semiconductors
C-2
PRELIMINARY INFORMATION
File: endian.fm5, modified 7/23/99
C.3
TEST TO VERIFY THE CORRECT
OPERATION OF TM1100 IN BIG AND
LITTLE ENDIAN SYSTEMS
The following test may be used to verify the correct oper-
ation of TM1100 in Little Endian and Big Endian systems.
1. Store a 32-bit constant “0x04050607” from the host
CPU to the TM1100’s SDRAM through PCI interface.
Load the word from the same address to one of the
TM1100’s global register and check for the same val-
ue.
2. Store a 32-bit constant “0x04050607” from the host
CPU to the TM1100’s SDRAM through PCI interface.
Load a byte from the same address to one of the
TM1100’s global register. Check for the value of
“0x04” in Big Endian systems, and check for the value
of “0x07” in Little Endian systems.
C.4
REQUIREMENT FOR THE TM1100 TO
OPERATE IN EITHER LITTLE ENDIAN
OR BIG ENDIAN MODE
The endian-ness handling in each unit is described in the
following sections. Most of the units use Highway/PCI
bus to transfer the data. The data format used in each
unit is shown when the data pass through the highway/
PCI bus. The highway/PCI bus has four byte lanes. The
bit assignment of the highway/PCI bus lanes is shown in
The PCI and TM1100’s highway buses are address in-
variant buses, i.e the data corresponds to address offset
“zero” uses the byte-0 lane of the PCI/Hwy bus, the data
corresponds to address offset “one” uses the byte-1 lane
of the PCI/Hwy bus etc.
C.4.1
Data Cache
TM1100’s PCSW register has a byte-sex (BSX) bit to
configure the TM1100 in Big Endian or Little Endian
mode. This bit needs to be set to ‘1’ for the Little Endian
This BSX bit is used by TM1100’s data cache unit for the
store/load operation from the data cache. Data Cache
performs three categories of data transactions:
Read/write data from/to DSPCPU registers to/from
Data Cache or SDRAM memory space.
Read/write of MMIO data from/to DSPCPU registers
to/from MMIO registers. and
Read/write data from/to DSPCPU registers to/from
PCI address space through special registers in the
BIU unit.
The DSPCPU’s endian-ness of operation is determined
by the value of the BSX bit in the PCSW register.
Tablebeing used by the data cache to transfer the data to/from
DSPCPU register to/from Data Cache or SDRAM.
Tablethe DRAM_BASE and DRAM_LIMIT range.
There is no byte-swap required for the MMIO data trans-
action from/to DSPCPU register to the MMIO registers.
However, one of the special register, PCI_DATA register
does not follow the normal MMIO transactions. The data
cache byte-swapes the data to/from the PCI_DATA reg-
ister using the data translation format as defined in
TableFor the configuration and I/O cycle transactions from
DSPCPU, programmer byte-swaps the data in DSPCPU
register and write to the PCI_DATA register using MMIO
write operation. There is no byte-swap from the
PCI_DATA register in BIU unit to the PCI bus. Software
data within the CPU register before writing the data to
PCI_DATA register for the configuration and I/O cycle
transactions.
Table C-1. Little Endian data format in TM1100 register, Highway, SDRAM memory, PCI bus, Host memory,
Host CPU register
PCSW-
BSX
value
Endian
Mode
Data Transaction
type
Address
Data in
DSPCPU
register
msb
lsb
Data in Highway/
Dcache/SDRAM/
PCI-bus
byte3
byte0
[31:24]
[7:0]
Data in Host
CPU register
msb
lsb
Data in Host
memory
byte3
byte0
[31:24]
[7:0]
1
Little
Word r/w
00001000
01020304
1
Little
Half-Word r/w
00001000
xxxx0304
1
Little
Half-Word r/w
00001002
xxxx0304
0304xxxx
xxxx0304
0304xxxx
1
Little
Byte read/write
00001000
xxxxxx04
1
Little
Byte read/write
00001001
xxxxxx04
xxxx04xx
xxxxxx04
xxxx04xx
1
Little
Byte read/write
00001002
xxxxxx04
xx04xxxx
xxxxxx04
xx04xxxx
1
Little
Byte read/write
00001003
xxxxxx04
04xxxxxx
xxxxxx04
04xxxxxx
Table C-2. Bit assignment of the highway/PCI bus
lanes
byte 3
byte 2
byte 1
byte 0
Bits
31:24
23:16
15:8
7:0