
File: sem.fm5, modified 7/23/99
PRELIMINARY INFORMATION
18-1
On-Chip Semaphore Assist Device
Chapter 18
TM1100 has a simple MP semaphore assist device. It is
an 32 bits register, accessible through MMIO by either
the local TM1100 CPU or by any other CPU on PCI
through the aperture made available on PCI. The sema-
phore “SEM” is located at MMIO offset 0x10 0500.
The operation is as follows: each master in the system
constructs a personal nonzero 12 bit ID (see below). To
obtain the global semaphore, a master does the follow-
ing action:
write ID to SEM (use 32 bit store, with ID in 12 LSB)
retrieve SEM
(use 32 bit load, it returns 0x00000nnn)
if (SEM = ID) {
“performs a short critical section action”
write 0 to SEM
}
else “try again later, or loop back to write”
18.1
SEM DEVICE SPECIFICATION
SEM is a 32 bits MMIO location. The 12 LSB consist of
storage flip-flops with surrounding logic, the 20 MSB's al-
ways return a zero when read.
SEM is RESET to zero by powerup reset.
When SEM is written to, the storage flip-flops behave as
follows:
if (cur_content == 0)
new_content = write_value;
else if (write_value == 0) new_content = 0;
/* ELSE NO ACTION ! */
18.2
CONSTRUCTING A 12-BIT ID
A TM1100 processor can construct a personal, nonzero
12 bit ID in a variety of ways. Below are some sugges-
tions.
PCI configspace PERSONALITY entry. Each TM1100
receives a 16 bits PERSONALITY value from the EE-
PROM during boot. This PERSONALITY register is lo-
cated at offset 0x40 in configuration space. In a MP sys-
tem, some of the bits of PERSONALITY can be
individualized for each CPU involved, giving it a unique
2/3/4 bit ID, as needed given the max. number of CPU's
in the design.
In the case of a host-assisted boot of TM1100, the PCI
BIOS assigns a unique MMIO_base and DRAM_base to
each and every TM1100. In particular, the 11 MSB's of
each MMIO_base are unique, since each MMIO aperture
is 2 MByte in size. These bits can be used as a person-
ality ID. Use bit 11 (MSB) equal '1' to guarantee a nonze-
ro ID#.
18.3
WHICH SEM TO USE
Each TM1100 in the system adds a SEM device to the
mix. The intended use is to treat one of these SEM de-
vices as THE master semaphore in the system. Many
methods can be used to determine which SEM is master
SEM. Some examples below:
Each DSPCPU can use PCI configurationspace access-
es to determine which other TM1100's are present in the
system. Then, the TM1100 with the lowest PERSONAL-
ITY number, or the lowest MMIO_base is chosen as the
TM1100 containing the master semaphore.
18.4
USAGE NOTES
To avoid contention on the master SEM device, it should
only be used for inter-processor semaphores. Processes
running on a single CPU can use regular memory to im-
plement synchronization primitives.
The critical section associated with SEM should be kept
as short as possible. Preferably, SEM should only be
used as the basis to make multiple memory resident sim-
ple semaphores. In this case, the non-cacheable DRAM
area of each TM1100 can be used to implement the
semaphore datastructures efficiently.
As described here, SEM does not guarantee starvation-
free access to critical resources. Claiming of SEM is
purely stochastical. This should work fine as long as
SEM is not overloaded. Utmost care should be taken in
SEM access frequency and duration of the basic critical
sections to keep the load conditions reasonable.
00000000000000000000
31
12 11
0
SEM
0x10 0500