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| 型號(hào)： | 935263151557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁(yè)數(shù)： | 23/518頁(yè) |
| 文件大?。?/td> | 7111K |
| 代理商： | 935263151557 |
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Philips Semiconductors
Video Out
File: evo.fm5, modified 7/24/99
PRELIMINARY INFORMATION
7-17
The VO unit is reset by the TM1100 hardware reset, or
by a software VO reset, as described in Table 7-7, RE-
SET bit.
The VO_CLK is normally set as output to drive the data
transfer for all modes at a programmable rate. The
VO_CLK signal can be an input or output, as controlled
by the CLKOUT bit in the VO_CTL register. When CLK-
OUT is set, VO_CLK is an output, and its frequency is set
by the VO_CLOCK register value. When CLKOUT is a
zero, VO_CLK is an input and the VO generates data at
the clock rate of the sender.
In video refresh modes, the VO receives or generates
horizontal and frame synchronization signals on the
VO_IO1 and VO_IO2 lines, as described in Section
7.14.1
Video Refresh Modes
In the video refresh modes, the VO transfers an image
from SDRAM to the VO port. The Mode field in the
VO_CTL register defines the video image memory data
format and whether the VO is to perform horizontal up-
scaling (see Table 7-5). The VO accepts memory image
data in YUV 4:2:2 co-sited, YUV 4:2:2 interspersed and
YUV 4:2:0 formats, and generates a CCIR 656 compati-
ble, YUV 4:2:2 co-sited image output stream. Scaling is
identified by the
YUV-1
× and YUV-2× modes. In YUV-1×
modes, luminance and chrominance pass unmodified. In
YUV-2
× modes, luminance and chrominance are hori-
zontally upscaled by a factor of two.
During video refresh, the YTR bit is set in the status reg-
ister when the Image Line Counter reaches the Y
THRESHOLD value. When an image field has been
transferred, the BFR1_EMPTY bit is set in the status reg-
ister. The DSPCPU is interrupted when either the YTR or
BFR1_EMPTY flag is set and its corresponding interrupt
is enabled. To maintain continuous transfer of image
fields, the DSP CPU supplies new pointers for the next
field following each BFR1_EMPTY interrupt. If the
DSPCPU does not supply new pointers before the next
field, the URUN bit is set, and the VO uses the same
pointer values until they are updated.
Graphics Overlay
The graphics overlay is enabled by the OL_EN bit in the
VO_CTL register. The graphics overlay is typically a soft-
ware-generated graphic overlaid onto the output video
image stream. The graphics overlay is either generated
in YUV by the DSPCPU or converted by the DSPCPU
from a RGB to a YUV overlay image. The DSPCPU per-
forms RGB to YUV conversion, because this conversion
can potentially lose information. Since the DSPCPU typ-
ically generates the image, the DSPCPU has the most
information about performing this conversion in the most
effective manner.
The overlay height should be chosen such that the over-
lay does not vertically extend beyond the image area. A
height greater than this causes undefined results and
may result in vertical overlay wraparound.
Note: The emitted byte data rate is limited to 45% of the
DRAM clock when overlays are enabled.
The YUV overlay logic assembles the U0, Y0, V0, Y1
bytes for a pair of YUV 4:2:2 pixels for both the main im-
age and the overlay image. The alpha bit for pixel 0 (the
LSB of the U0 byte of the overlay image) selects ALPHA
ZERO or ALPHA ONE as the alpha source, and the al-
pha blend logic combines U0, Y0, and V0 from the main
and overlay images to generate the U0, Y0 and V0 out-
put values. The alpha bit for pixel 1 (the LSB of the V0
byte of the overlay image) selects ALPHA ZERO or AL-
PHA ONE as the alpha source for blending the Y1 pixels
to generate the Y1 output value. The alpha blended U0,
Y0, V0 and Y1 bytes are sent to the VO output port in the
YUV 422 sequence. The overlay U and V values used
assume a LSB of zero.
Video Image Addressing
The output image is read from SDRAM at a location de-
fined by Y_BASE_ADR, Y_OFFSET, U_BASE_ADR,
U_OFFSET, V_BASE_ADR, and V_OFFSET. The de-
fault memory packing is big-endian although little-endian
packing is also supported by setting the LTL_END bit in
the VO_CTL register.
Horizontally adjacent samples are stored at successive
byte addresses, resulting in a packed form (four 8-bit
samples are packed into one 32-bit word). Upon horizon-
tal retrace, the starting byte address for the next line is
computed by adding the corresponding OFFSET value
to the previous line’s starting byte address. Note that
OFFSET is a 16-bit unsigned quantity. This process con-
tinues until the total image—height in lines and width in
pixels per line—have been read from memory for lumi-
nance (Y). For chrominance, the same number of lines
Table 7-9. Timing Register Recommended Values
Register
Field
525/60 Value
625/50 Value
VO_CLOCK
FREQUENCY
170A3D70h
VO_FRAME
FRAME-
LENGTH
525
625
FIELD 2
START
264
311
FRAME PRE-
SET
11
VO_FIELD
F1 VIDEO
LINE
20
23
F2 VIDEO
LINE
283
336
F1 OLAP
2
F2 OLAP
3
-2 (0xE)
VO_LINE
FRAME
WIDTH
858
864
VIDEO PIXEL
START
138
144
VO_IMAGE
IMAGE
HEIGHT
240
288
IMAGE WIDTH
720
(704 visible)
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