
TM1100 Preliminary Data Book
Philips Semiconductors
B-4
PRELIMINARY INFORMATION
File: mmio.fm5, modified 7/23/99
AI_FREQ
10 1c10
R/W
Sets AI_OSCLK frequency
AI_BASE1
10 1c14
R/W
Sets base address of buffer 1
AI_BASE2
10 1c18
R/W
Sets base address of buffer 2
AI_SIZE
10 1c1c
R/W
Sets number of samples in buffers
Audio Out
AO_STATUS
10 2000
R/—
Status of audio-out unit
AO_CTL
10 2004
R/W
Sets operation and interrupt modes for audio out
AO_SERIAL
10 2008
R/W
Sets clock ratios and internal/external clock generation
AO_FRAMING
10 200c
R/W
Sets format of serial data stream
AO_FREQ
10 2010
R/W
Set AO_OSCLK frequency
AO_BASE1
10 2014
R/W
Sets base address of buffer 1
AO_BASE2
10 2018
R/W
Sets base address of buffer 2
AO_SIZE
10 201c
R/W
Sets number of samples in buffers
AO_CC
10 2020
R/W
Codec control eld values
AO_CFC
10 2024
R/W
Codec Frame Control
PCI Interface
BIU_STATUS
10 3004
R/—
Status of PCI interface (done/busy bits, error bits)
BIU_CTL
10 3008
R/W
Sets operation and interrupt modes for PCI
PCI_ADR
10 300c
R/W
—/—
Holds address for DSPCPU PCI access
PCI_DATA
10 3010
R/W
—/—
Holds data for DSPCPU PCI access
CONFIG_ADR
10 3014
R/W
Holds address for conguration access
CONFIG_DATA
10 3018
R/W
Holds data for conguration access
CONFIG_CTL
10 301c
R/W
Sets read/write, bus number for conguration access
IO_ADR
10 3020
R/W
Holds address for I/O access
IO_DATA
10 3024
R/W
Holds data for I/O access
IO_CTL
10 3028
R/W
Sets read/write, byte-enable for I/O access
SRC_ADR
10 302c
R/W
Holds source address for DMA operation
DEST_ADR
10 3030
R/W
Holds destination address for DMA operation
DMA_CTL
10 3034
R/W
Sets read/write, transfer length for DMA operation
INT_CTL
10 3038
R/W
Controls interrupt system
XIO_CTL
10 3060
R/W
XIO control register
JTAG
JTAG_DATA_IN
10 3800
R/W
JTAG data input buffer
JTAG_DATA_OUT
10 3804
R/W
JTAG data output buffer
JTAG_CTL
10 3808
R/W
JTAG control
Image Co-Processor
ICP_MPC
10 2400
R/W
MicroProgram Counter
ICP_MIR
10 2404
R/W
Micro Instruction Register
ICP_DP
10 2408
R/W
Data Pointer
ICP_DR
10 2410
R/W
Data Register
ICP_SR
10 2414
R/W
Status Register
VLD Co-Processor
VLD_COMMAND
10 2800
R/W
Next action to be taken by VLD
VLD_SR
10 2804
R/—
Bitstream shift register
VLD_QS
10 2808
R/W
Quantization Scale Code
MMIO Register Name
Offset
(in hex)
Accessibility
Description
DSPCPU
External
PCI
Initiators