
File: aout.fm5, modified 7/24/99
PRELIMINARY INFORMATION
9-1
Audio Out
Chapter 9
by Gert Slavenburg, Patrick de Bakker, Charles Peplinski
9.1
AUDIO OUT OVERVIEW
The TM1100 Audio Out unit connects to one to four off-
chip stereo D/A converters through a flexible bit-serial
connection. Audio Out provides all signals to interface to
high quality, low cost oversampling D/A converters, in-
cluding a precisely programmable oversampling D/A
system clock. The Audio Out unit and external D/A to-
gether provide the following capabilities:
Up to 8 channels of audio output.
Eight- or 16-bit samples per channel.
Programmable sampling rate
Internal or external sampling clock source.
Audio Out autonomously reads processed audio data
from memory using double buffering (DMA).
Eight-bit mono and stereo as well as 16-bit mono and
stereo PC standard memory data formats are sup-
ported.
Little- and big-endian memory formats are sup-
ported.
Provides control capability for highly integrated PC
codecs such as the AD1847 and CS4218.
9.2
NEW IN TM1100
improved internal clock source with less jitter
9.3
EXTERNAL INTERFACE
Four TM1100 pins are associated with the Audio Out
unit. The AO_OSCLK output is an accurately program-
mable clock output intended to be used as the master
system clock for the external D/A subsystem. The other
three pins (AO_SCK, AO_WS and AO_SD) constitute a
flexible serial output interface. Using the Audio Out
MMIO registers, these pins can be configured to operate
in a variety of serial interface framing modes, including
but not limited to:
Standard stereo I2S (MSB rst, one-bit delay from
AO_WS, left & right data in a frame).
LSB rst, with 1–16 bit data per channel.
Complex serial frames of up to 512 bits/frame.
Superframes of up to 4 regular frames can be cre-
ated for 4,6 or 8 channel modes.
Table 9-1. Audio-Out Unit External Signals
Signal
Type
Description
AO_OSCLK
OUT
Oversampling Clock. This output can
be programmed to emit any frequency
up to 40 MHz, with a resolution of 0.07
Hz. It is intended for use as the 256 or
384fs oversampling clock by the exter-
nal D/A conversion subsystem.
AO_SCK
I/O-5
When Audio Out is programmed to
act as the serial interface timing
slave (RESET default), AO_SCK
acts as input. It receives the Serial
Clock from the external audio D/A
subsystem. The clock is treated as
fully asynchronous to the TM1100
main clock.
When Audio Out is programmed to
act as serial interface timing master,
AO_SCK acts as output. It drives
the Serial Clock for the external
audio D/A subsystem. The clock
frequency is a programmable inte-
gral divide of the AO_OSCLK fre-
quency.
AO_SCK is limited to 20 MHz. The
sample rate of valid samples embed-
ded within the serial stream is also lim-
ited by the bandwidth.latency available
AO_SD
OUT-5
Serial Data to external audio D/A sub-
system. The timing of transitions on
this output is determined by the
CLOCK_EDGE bit in the AO_SERIAL
register, and can be on positive or neg-
ative AO_SCK edges.
AO_WS
I/O-5
When Audio-Out is programmed as
the serial-interface timing slave
(RESET default), AO_WS acts as
an input. AO_WS is sampled on the
opposite AO_SCK edge at which
AO_SD is asserted.
When Audio Out is programmed as
serial-interface timing master,
AO_WS acts as an output. AO_WS
is asserted on the same AO_SCK
edge as AO_SD.
AO_WS is the word-select or frame-
synchronization signal from/to the
external D/A subsystem. Each audio
channel receives 1 sample for every
WS period.