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參數(shù)資料
| 型號： | 935262469557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封裝： | 32 X 32 MM, 3.40 MM HEIGHT, MSQFP-240 |
| 文件頁數(shù)： | 118/518頁 |
| 文件大小： | 7111K |
| 代理商： | 935262469557 |
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TM1100 Preliminary Data Book
Philips Semiconductors
13-18
PRELIMINARY INFORMATION
File: icp.fm5, modified 7/26/99
The PD eld sets a timer for bus activity that denes
the minimum bus bandwidth available to the ICP.
The PWDN bit indicates a selective power down of
the ICP.
The ICP Status Register contains 20 read only status
bits. The upper 16 bits of the Status Register can contain
a 16-bit code returned by the microprogram upon com-
pletion. Bits 15 through 12 are reserved for error flags.
Bit 31 has a special function as PWDN bit in TM1100
only. It is reserved in future implementations. To use this
TM1100 feature the microprogram writes a 1 into PWDN.
After the busy bit is removed the ICP will power down. It
is only powered up again by a hardware reset. See also
Chapter 20 for Power Management features. Note: the
PWDN bit can only be written by the microprogram.
Important Note: You must set the ICP DMA Enable bit
(IE) in the BIU_CTL register of the PCI interface for RGB
output to PCI. This bit must be set before initiating RGB
to PCI operations, or the ICP will stall waiting for the PCI
to become ready. Refer to Section 10.7.5, “BIU_CTL
13.6.2
ICP Operation
The DSPCPU commands the ICP to perform an opera-
tion by loading the DP with a pointer to a parameter
block, loading the MPC with a microprogram start ad-
dress and setting Busy in the SR. For example to cause
the ICP to scale and filter an image, you set up a block of
SDRAM with the image and filter parameters, load the
MPC with the starting address of the appropriate micro-
program entry point in SDRAM, load the DP with the ad-
dress of the parameter block, and set Busy in the SR by
writing a one to it. When the filter operation is complete,
the ICP will set Done and issue an interrupt. The
DSPCPU clears the interrupt by writing a one to
ACK_DONE. Note: The interrupt should be set up as a
level triggered interrupt.
When the DSPCPU sets busy, the MCU begins reading
the microprogram from SDRAM. The microinstructions
are read in from SDRAM as required by the ICP, and in-
ternal pre-fetching is used to eliminate delays. Setting
Busy enables the MCU clock, the first block of microin-
structions is automatically read in and the MCU begins
instruction execution at the current address in the MPC.
Clearing Busy stops the MCU clock. Busy can be cleared
by hardware reset, by the MCU and by the DSPCPU.
Hardware reset clears the Status register, including Busy
and Done, and internal registers, such as the TCR.
When the MCU completes a microprogram operation,
the microprogram typically clears Busy and sets Done,
causing an interrupt if IE is enabled.
The DSPCPU performs a software reset by clearing
(writing a zero to) Busy and by writing a one to Reset.
The DSPCPU can also set Done to force a hardware in-
terrupt, if desired.
13.6.3
ICP Microprogram Set
The ICP comes with a factory generated microprogram
set. This microprogram set implements the functions of
the ICP. The microprogram set includes the following
functions:
1. Loading the lter coefcient RAMs.
2. Horizontal scaling and ltering from SDRAM to
SDRAM of an input image to an output image. The in-
put and output images can be of any size and position
that ts in SDRAM.The scaling factors are, in general,
limited only by input and output image sizes.
3. Vertical scaling and ltering from SDRAM to SDRAM
of an input image to an output image. The input and
output images can be of any size and position that ts
in SDRAM. The scaling factors are, in general, limited
only by input and output image sizes.
4. Horizontal scaling, ltering and YUV to RGB conver-
sion of an input image from SDRAM to an output im-
age to PCI or SDRAM, with an alpha blended and
chroma keyed RGB overlay and a bit mask. The input
and output images can be of any size and position
that ts in SDRAM and output to the PCI bus or
SDRAM, The scaling factors are, in general, limited
only by input and output image sizes.
The microprogram is supplied with the ICP as part of the
device driver. The entry point in the microprogram de-
fines which ICP operation is to be done. The entry points
are given below in terms of word offsets from the begin-
ning of the microprogram:
Offset
Function
0
Load coefcients
1
Horizontal scaling and ltering
2
Vertical scaling and ltering
3
Horizontal scaling, ltering, YUV to RGB
conversion, bit masking (PCI) and over-
lay (PCI) with alpha blending and
chroma keying
13.6.4
ICP Processing Time
The processing time for typical operations on typical pic-
ture sizes has been measured.
During the measurements the CPU clock and SDRAM
clock were set to 100MHz, PCI clock was 33MHz. All
measurement with PCI as pixel destination were done
with an Imagine 128 Series II graphics card, which never
caused a slowdown of the ICP operation. The mother-
board
was
a
TRITON2
with
SB82437UX
and
SB82371SB based Intel Pentium
chipset. The
TM1100 arbiter was set to default settings. TM1100 la-
tency timer was set to maximum value = 0xf8.
Overlay sizes were the same as picture sizes.
The results are tabulated below for three different cases
of available memory bandwidth:
1. No other load to SDRAM, i.e. full SDRAM bandwidth
available for ICP. See Table 13-5
2. SDRAM memory loaded to 95% of its bandwidth by
DCACHE traffic from DSPCPU. Priority delay = 1, i.e.
ICP did wait one block time before competing for memo-
ry. See Table 13-6
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