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參數(shù)資料
| 型號： | 8XC562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 6/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC562 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
6
T2MS0
BIT
TM2CON.7
TM2CON.6
TM2CON.5
SYMBOL
TSIS1
T2IS0
T2ER
FUNCTION
Timer T2 16-bit overflow interrupt select
Timer T2 byte overflow interrupt select
Timer T2 external reset enable. When this bit is set,
Timer T2 may be reset by a rising edge on RT2 (P1.5).
Timer T2 byte overflow interrupt flag
TM2CON.4
TM2CON.3
TM2CON.2
T2BO
T2P1
T2P0
TM2CON.1
TM2CON.0
T2MS1
T2MS0
SU00756
T2MS1
T2P0
T2P1
T2BO
T2ER
T2IS0
T2IS1
0
1
2
3
4
5
6
7
(LSB)
(MSB)
TM2CON (EAH)
Timer T2 prescaler select
T2P1
0
0
1
1
T2P0
0
1
0
1
Timer T2 Clock
Clock source
Clock source/2
Clock source/4
Clock source/8
Timer T2 mode select
0
0
1
1
0
1
0
1
Timer T2 halted (off)
T2 clock source = f
OSC
/12
Test mode; do not use
T2 clock source = pin T2
T2MS1
T2MS0
Mode Selected
Figure 3. T2 Control Register (TM2CON)
Timer T2 Extension:
When a 12MHz oscillator is used, a 16-bit
overflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms,
depending on the prescaler division ratio; i.e., the maximum cycle
time is approximately 0.5 seconds. In applications where cycle times
are greater than 0.5 seconds, it is necessary to extend Timer T2.
This is achieved by selecting fosc/12 as the clock source (set
T2MS0, reset T2MS1), setting the prescaler division ration to 1/8
(set T2P0, set T2P1), disabling the byte overflow interrupt (reset
T2IS0) and enabling the 16-bit overflow interrupt (set T2IS1). The
following software routine is written for a three-byte extension which
gives a maximum cycle time of approximately 2400 hours.
OVINT: PUSH
ACC
PSW
TIMEX1
;save accumulator
;save status
;increment first byte (low order)
;of extended timer
PUSH
INC
MOV
JNZ
A,TIMEX1
INTEX
;jump to INTEX if ;there is no overflow
INC
MOV
JNZ
INC
TIMEX2
A,TIMEX2
INTEX
TIMEX3
;increment second byte
;jump to INTEX if there is no overflow
;increment third byte (high order)
INTEX: CLR
T2OV
PSW
ACC
;reset interrupt flag
;restore status
;restore accumulator
;return from interrupt
POP
POP
RETI
Timer T2, Capture and Compare Logic:
Timer T2 is connected to
four 16-bit capture registers and three 16-bit compare registers. A
capture register may be used to capture the contents of Timer T2
when a transition occurs on its corresponding input pin. A compare
register may be used to set, reset, or toggle port 4 output pins at
certain pre-programmable time intervals.
The combination of Timer T2 and the capture and compare logic is
very powerful in applications involving rotating machinery,
automotive injection systems, etc. Timer T2 and the capture and
compare logic are shown in Figure 4.
Capture Logic:
The four 16-bit capture registers that Timer T2 is
connected to are: CT0, CT1, CT2, and CT3. These registers are
loaded with the contents of Timer T2, and an interrupt is requested
upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These
input signals are shared with port 1. The four interrupt flags are in
the Timer T2 interrupt register (TM2IR special function register). If
the capture facility is not required, these inputs can be regarded as
additional external interrupt inputs.
Using the capture control register CTCON (see Figure 5), these
inputs may capture on a rising edge, a falling edge, or on either a
rising or falling edge. The inputs are sampled during S1P1 of each
cycle. When a selected edge is detected, the contents of Timer T2
are captured at the end of the cycle.
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