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參數(shù)資料
| 型號： | 8XC562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 55/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC562 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
55
SMOD
–
–
WLE
GF1
GF0
PD
IDL
7
6
5
4
3
2
1
0
PCON
(87H)
PCON.7
SMOD
Double Baud rate bit. When set to logic 1 the
baud rate is doubled when the serial port SIO0
is being used in modes 1, 2, or 3.
(Reserved)
(Reserved)
Watchdog load enable. This flag must be set
by software prior to loading timer T3 (watch-
dog timer). It is cleared when timer T3 is
loaded.
General-purpose flag bit
General-purpose flag bit
Power-down bit. Setting this bit activates the
power-down mode. It can only be set if input
EW is high.
Idle mode bit. Setting this bit activates the idle
mode.
PCON.6
PCON.5
PCON.4
–
–
WLE
PCON.3
PCON.2
PCON.1
GF1
GF0
PD
PCON.0
IDL
BIT
SYMBOL
FUNCTION
If logic 1s are written to PD and IDL at the
same time, PD takes precedence. The reset
value of PCON is (0XX00000).
Figure 41. Power Control Register (PCON)
255
255
Upper
128 Bytes
Internal RAM
Special
Function
Registers
Indirect
Addressing
Only
Direct
Addressing
Only
128
Direct or
Indirect
Addressing
Overlapped
Space
127
48
127
120
32
7
R7
0
24
R0
R7
Bank 3
16
R0
R7
Bank 2
8
R0
R7
Bank 1
0
R0
Bank 1
Addressable
Bits in RAM
(128 Bits)
Registers
Internal
Data RAM
Figure 42. Internal Data Memory Address Space
ARITHMETIC REGISTERS:
ACCumulator,* B register,*
Program Status Word*
POINTERS:
Stack Pointer,
Data Pointer (High and Low)
PARALLEL I/O PORTS:
Port 5,* Port 4,*Port 3,*
Port 2,* Port 1,* Port 0*
INTERRUPT SYSTEM:
Interrupt Priority 0,*
Interrupt Priority 1,*
Interrupt Enable 0,*
Interrupt Enable 1*
PULSE WIDTH MODULATED O/Ps:
Pulse Width Modulation Prescaler
Pulse Width Modulation Register 0,
Pulse Width Modulation Register 1
SERIAL I/O PORTS:
Serial 0 CONtrol,* Serial 0 data BUFfer,
Serial 1 CONtrol,* Serial 1 DATa,
Serial 1 STAtus, Serial 1 ADDress, PCON
TIMERS:
Timer MODe, Timer CONtrol,*
Timer Low 0, Timer High 0,
Timer Low 1, Timer High 1,
TiMer T2 CONtrol, TiMer Low 2,
Timer High 2, Timer T3
CAPTURE AND COMPARE LOGIC:
CapTure CONtrol,
TiMer T2 Interrupt flag Register,
CapTure Low 0, CapTure High 0,
CapTure Low 1, CapTure High 1,
CapTure Low 2, CapTure High 2,
CapTure Low 3, CapTure High 3,
CoMpare Low 0, CoMpare High 0,
CoMpare Low 1, CoMpare High 1,
CoMpare Low 2, CoMpare High 2
SeT Enable, ReseT Enable
ADC
ADC cONtrol, ADC High byte
*NOTE: Bit and byte addressable
Figure 43. Special Function Registers
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| 8XC552 | 80C51 FAMILY DERIVATIVES |
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