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| 型號(hào)： | 8XC562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 10/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC562 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
10
Internal Bus
Timer T3 (8-bit)
LOAD LOADEN
Prescaler (11-bit)
Clear
f
OSC
/12
EW
WLE
Clear
PD
LOADEN
RST
R
RST
V
DD
P
Internal
reset
Internal Bus
Write T3
PCON.4
PCON.1
Overflow
Figure 9. Watchdog Timer
The watchdog timer is reloaded in two stages in order to prevent
erroneous software from reloading the watchdog. First PCON.4
(WLE) must be set. The T3 may be loaded. When T3 is loaded,
PCON.4 (WLE) is automatically reset. T3 cannot be loaded if
PCON.4 (WLE) is reset. Reload code may be put in a subroutine as
it is called frequently. Since Timer T3 is an up-counter, a reload
value of 00H gives the maximum watchdog interval (510ms with a
12MHz oscillator), and a reload value of 0FFH gives the minimum
watchdog interval (2ms with a 12MHz oscillator).
In the idle mode, the watchdog circuitry remains active. When
watchdog operation is implemented, the power-down mode cannot
be used since both states are contradictory. Thus, when watchdog
operation is enabled by tying external pin EW low, it is impossible to
enter the power-down mode, and an attempt to set the power-down
bit (PCON.1) will have no effect. PCON.1 will remain at logic 0.
During the early stages of software development/debugging, the
watchdog may be disabled by tying the EW pin high. At a later
stage, EW may be tied low to complete the debugging process.
Watchdog Software Example:
The following example shows how
watchdog operation might be handled in a user program.
;at the program start:
T3
PCON
WATCH-INTV EQU 156
EQU 0FFH ;address of watchdog timer T3
EQU 087H ;address of PCON SFR
;watchdog interval (e.g., 2x100ms)
;to be inserted at each watchdog reload location within
;the user program:
LCALL WATCHDOG
;watchdog service routine:
WATCHDOG: ORL PCON,#10H ;set condition flag (PCON.4)
MOV T3,WATCH-INV
RET
;load T3 with watchdog interval
If it is possible for this subroutine to be called in an erroneous state,
then the condition flag WLE should be set at different parts of the
main program.
Serial I/O
The 8XC552 is equipped with two independent serial ports: SIO0
and SIO1. SIO0 is a full duplex UART port and is identical to the
80C51 serial port. SIO1 accommodates the I
2
C bus.
SIO0:
SIO0 is a full duplex serial I/O port identical to that on the
80C51. Its operation is the same, including the use of timer 1 as a
baud rate generator.
SIO1, I
2
C Serial I/O:
The I
2
C bus uses two wires (SDA and SCL) to
transfer information between devices connected to the bus. The
main features of the bus are:
– Bidirectional data transfer between masters and slaves
– Multimaster bus (no central master)
– Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
– Serial clock synchronization allows devices with different bit rates
to communicate via one serial bus
– Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer
– The I
2
C bus may be used for test and diagnostic purposes
The output latches of P1.6 and P1.7 must be set to logic 1 in order
to enable SIO1.
The 8XC552 on-chip I
2
C logic provides a serial interface that meets
the I
2
C bus specification and supports all transfer modes (other than
the low-speed mode) from and to the I
2
C bus. The SIO1 logic
handles bytes transfer autonomously. It also keeps track of serial
transfers, and a status register (S1STA) reflects the status of SIO1
and the I
2
C bus.
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