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參數(shù)資料
| 型號： | 8XC562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 FAMILY DERIVATIVES |
| 中文描述： | 80C51系列衍生物 |
| 文件頁數(shù)： | 54/60頁 |
| 文件大?。?/td> | 382K |
| 代理商： | 8XC562 |
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Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
1996 Aug 06
54
Power-Down Mode:
The instruction that sets PCON.1 will be the
last instruction executed in the normal operating mode before the
power-down mode is entered. In the power-down mode, the on-chip
oscillator is stopped. This freezes all functions; only the on-chip
RAM and special function registers are held. The port pins output
the contents of their respective special function registers. A
hardware reset is the only way to terminate the power-down mode.
Reset re-defines all the special function registers, but does not
change the on-chip RAM.
In the power-down mode, V
DD
and AV
DD
can be reduced to
minimize power consumption. V
DD
and AV
DD
must not be reduced
before the power-down mode is entered and must be restored to the
normal operating voltage before the power-down mode is
terminated. The reset that terminates the power-down mode also
freezes the oscillator. The reset should not be activated before V
DD
and AV
DD
are restored to their normal operating level, and must be
held active long enough to allow the oscillator to restart and stabilize
(normally less than 10ms).
The status of the external pins during power-down is shown in Table
11. If the power-down mode is entered while the 8XC552 is
executing out of external program memory, the port data that is held
in the P2 special function register is restored to port 2. If a port latch
contains a “1”, the port pin is held HIGH during the power-down
mode by the strong pull-up transistor.
Power Control Register PCON:
The idle and power-down modes
are entered by writing to bits in PCON. PCON is not bit addressable.
See Figure 41.
Memory Organization
The memory organization of the 8XC552 is the same as in the
80C51, with the exception that the 8XC552 has 8k ROM, 256 bytes
RAM, and additional SFRs. Addressing modes are the same in the
8XC552 and the 80C51. Details of the differences are given in the
following paragraphs.
In the 8XC552, the lower 8k of the 64k program memory address
space is filled by internal ROM. By tying the EA pin high, the
processor fetches instructions from internal program ROM. Bus
expansion for accessing program memory from 8k upwards is
automatic since external instruction fetches occur automatically
when the program counter exceeds 8191. If the EA pin is tied low, all
program memory fetches are from external memory. The execution
speed of the 8XC552 is the same regardless of whether fetches are
from external or internal program memory. If all storage is on-chip,
then byte location 8191 should be left vacant to prevent an
undesired pre-fetch from external program memory address 8192.
Certain locations in program memory are reserved for specific
programs. Locations 0000H to 0002H are reserved for the
initialization program. Following reset, the CPU always begins
execution at locations 0000H. Locations 0003H to 0075H are
reserved for the fifteen interrupt request service routines.
Functionally, the internal data memory is the most flexible of the
address spaces. The internal data memory space is subdivided into
a 256-byte internal data RAM address space and a 128-byte special
function register (SFR) address space, as shown in Figure 42.
The internal data RAM address space is 0 to 255. Four 8-bit register
banks occupy locations 0 to 31. 128 bit locations of the internal data
RAM are accessible through direct addressing. These bits reside in
16 bytes of internal data RAM at locations 20H to 2FH. The stack
can be located anywhere in the internal data RAM address space by
loading the 8-bit stack pointer. The stack depth may be 256 bytes
maximum.
The SFR address space is 128 to 255. All registers except the
program counter and the four 8-bit register banks reside in this
address space. Memory mapping the SFRs allows them to be
accessed as easily as internal RAM, and as such, they can be
operated on by most instructions. The 56 SFRs are listed in Figure
43, and their mapping in the SFR address space is shown in Figures
44 and 45. RAM bit addresses are the same as in the 80C51 and
are summarized in Figure 46. The special function bit addresses are
summarized in Figure 47.
Table 11.
External Pin Status During Idle and Power-Down Modes
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PWM0/PWM1
Idle (1)
Internal
1
1
Port data
Port data
Port data
Port data
Port data
HIGH
Idle (1)
External
1
1
Floating
Port data
Address
Port data
Port data
HIGH
Power-down
Internal
0
0
Port data
Port data
Port data
Port data
Port data
HIGH
Power-down
External
0
0
Floating
Port data
Port data
Port data
Port data
HIGH
相關PDF資料 |
PDF描述 |
|---|---|
| 8XC552 | 80C51 FAMILY DERIVATIVES |
| 8XL51FB | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL51FC | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL51FA | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
| 8XL54 | LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 8XC58 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 8XC80C32 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit CMOS (low voltage, low power and high speed) microcontroller families |
| 8XF0016-S3P | 制造商:XFMRS 制造商全稱:XFMRS Inc. 功能描述:INDUCTOR |
| 8XF0106-S3P | 制造商:XFMRS 制造商全稱:XFMRS Inc. 功能描述:INDUCTOR |
| 8XF0156-S3P | 制造商:XFMRS 制造商全稱:XFMRS Inc. 功能描述:INDUCTOR |
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