參數(shù)資料
型號(hào)： 854S057BGILF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： LOW SKEW CLOCK DRIVER, PDSO20
封裝： ROHS COMPLIANT, MO-153, TSSOP-20
文件頁(yè)數(shù)： 8/15頁(yè)
文件大小： 761K
代理商： 854S057BGILF
ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
ICS854S057BGI REVISION A MARCH 29, 2010
2
2010 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Table 3. Control Input Function Table
Number
Name
Type
Description
1, 20
VDD
Power
Power supply pins.
2
PCLK0
Input
Non-inverting LVPECL differential clock input. RT = 50 termination to VT0.
3
VT0
Input
Termination input. For LVDS input, leave floating. RT = 50 termination to VT0.
4
nPCLK0
Input
Inverting LVPECL differential clock input. RT = 50 termination to VT0.
5, 6
SEL1, SEL0
Input
Pulldown
Clock select inputs. LVCMOS/LVTTL interface levels.
7
PCLK1
Input
Non-inverting LVPECL differential clock input. RT = 50 termination to VT1.
8
VT1
Input
Termination input. For LVDS input, leave floating. RT = 50 termination to VT1.
9
nPCLK1
Input
Inverting LVPECL differential clock input. RT = 50 termination to VT1.
10, 11
GND
Power
Power supply ground.
12
nPCLK2
Input
Inverting LVPECL differential clock input. RT = 50 termination to VT2.
13
VT2
Input
Termination input. For LVDS input, leave floating. RT = 50 termination to VT2.
14
PCLK2
Input
Non-inverting LVPECL differential clock input. RT = 50 termination to VT2.
15, 16
nQ, Q
Output
Differential output pair. LVDS interface levels.
17
nPCLK3
Input
Inverting LVPECL differential clock input. RT = 50 termination to VT3.
18
VT3
Input
Termination input. For LVDS input, leave floating. RT = 50 termination to VT3.
19
PCLK3
Input
Non-inverting LVPECL differential clock input. RT = 50 termination to VT3.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
2pF
RPULLDOWN Input Pulldown Resistor
50
k
RT
Input Termination Resistor
40
50
60
Inputs
Outputs
SEL1
SEL0
PCLKx, nPCLKx
0
PCLK0, nPCLK0
0
1
PCLK1, nPCLK1
1
0
PCLK2, nPCLK2
1
PCLK3, nPCLK3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
854S057BGILFT 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 4-IN LVDS 20-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:20 TSSOP (LEAD-FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:4:1 or 2:1 LVDS Clk Multiplexer w/int
854S058AGILF 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
854S058AGILFT 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 8-IN LVDS 24-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:SMALL SIGE ARRAY - Bulk 制造商:Integrated Device Technology Inc 功能描述:DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX
854S1208AYILF 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVDS 48-Pin TQFP EP Tray 制造商:Integrated Device Technology Inc 功能描述:CLOCK MLTPLXR - Trays
854S1208AYILFT 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVDS 48-Pin TQFP EP T/R
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