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參數(shù)資料
| 型號： | 854S057BGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO20 |
| 封裝： | ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 761K |
| 代理商： | 854S057BGILF |
ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
ICS854S057BGI REVISION A MARCH 29, 2010
10
2010 Integrated Device Technology, Inc.
LVDS Driver Termination
A general LVDS interface is shown in Figure 3. Standard termination
for LVDS type output structure requires both a 100
parallel resistor
at the receiver and a 100
differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 3 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
Figure 3. Typical LVDS Driver Termination
Schematic Example
Figure 4 shows a schematic example of the ICS854S057BI. In this
example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are used.
The decoupling capacitors should be physically located near the
power pin.
Figure 4. ICS854S057BI LVDS Schematic Example
100
–
+
100
Differential Transmission Line
LVDS Driver
LVDS
Receiver
(U1,20)
R2
680
Zo = 50
VDD
R3
680
Zo = 50
R5
100
R1
680
U1
ICS854057
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
nPCLK2
VT2
PCLK2
nQ
Q
VDD
PCLK3
VT3
nPCLK3
Zo = 50
VDD
LVDS
+
-
R4
680
R6
18
Zo = 50
VDD
VDD=2.5V
LVDS
R1
1K
LVPECL
C2
0.1u
(U1,1)
R1
1K
C1
0.1u
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 854S057BGILFT | 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 4-IN LVDS 20-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:20 TSSOP (LEAD-FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:4:1 or 2:1 LVDS Clk Multiplexer w/int |
| 854S058AGILF | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| 854S058AGILFT | 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 8-IN LVDS 24-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:SMALL SIGE ARRAY - Bulk 制造商:Integrated Device Technology Inc 功能描述:DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX |
| 854S1208AYILF | 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVDS 48-Pin TQFP EP Tray 制造商:Integrated Device Technology Inc 功能描述:CLOCK MLTPLXR - Trays |
| 854S1208AYILFT | 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVDS 48-Pin TQFP EP T/R |
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