- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄298597 > 854S057BGILF (INTEGRATED DEVICE TECHNOLOGY INC) LOW SKEW CLOCK DRIVER, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | 854S057BGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO20 |
| 封裝： | ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁(yè)數(shù)： | 11/15頁(yè) |
| 文件大?。?/td> | 761K |
| 代理商： | 854S057BGILF |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
ICS854S057BGI REVISION A MARCH 29, 2010
5
2010 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rohde & Schwarz SMA100A Low Noise
Signal Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
SSB
Phas
e
Noise
dBc/Hz
Offset from Carrier Frequency (Hz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 855-075-1 | 75 CONTACT(S), FEMALE, STRAIGHT SINGLE PART CARD EDGE CONN, SOLDER |
| 85514-001 | 20 CONTACT(S), STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER |
| 85514-002 | 12 CONTACT(S), STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER |
| 85514-003 | 2 CONTACT(S), STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER |
| 85656-001LF | 25 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 854S057BGILFT | 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 4-IN LVDS 20-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:20 TSSOP (LEAD-FREE) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:4:1 or 2:1 LVDS Clk Multiplexer w/int |
| 854S058AGILF | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| 854S058AGILFT | 制造商:Integrated Device Technology Inc 功能描述:Clock Multiplexer 8-IN LVDS 24-Pin TSSOP T/R 制造商:Integrated Device Technology Inc 功能描述:SMALL SIGE ARRAY - Bulk 制造商:Integrated Device Technology Inc 功能描述:DIFFERENTIAL-TO-LVDS 8:1 CLOCK MULTIPLEX |
| 854S1208AYILF | 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVDS 48-Pin TQFP EP Tray 制造商:Integrated Device Technology Inc 功能描述:CLOCK MLTPLXR - Trays |
| 854S1208AYILFT | 制造商:Integrated Device Technology Inc 功能描述:Clock Driver 2-IN LVDS 48-Pin TQFP EP T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。