參數(shù)資料
型號(hào)： 8502
廠商： LSI Corporation
英文描述： Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器)
中文描述： 以太網(wǎng)MII（媒體獨(dú)立接口）的投資者聯(lián)盟（連接單元接口）接口適配器（以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器）
文件頁數(shù)： 25/55頁
文件大?。?/td> 457K
代理商： 8502
8502
4-25
MD400157/D
3.19.5 Timing
The total EEI cycle consists of six individual EE_CS
cycles, one for each register accessed over the EEI.
Before a reset s nitiated, the EEI s n the dle state. During
idle, EE_CS=0, EE_DO is in the high impedance state,
EE_DI is ignored, and EE_CLK clock output is held low.
When a reset is initiated, then EE_CS is asserted high,
EE_CLK clock output is enabled, and a serial shift cycle is
initiated between the external EEPROM and the 8502.
Data on EE_DO is then shifted out from the 8502 to the
EEPROM on the first 9 falling edges of EE_CLK. On the
next 16 falling edges of EE_CLK, data is shifted into the
8502 from the EEPROM on EE_DI (EE_DO is high
impedance). After 25 EE_CLK cycles have been com-
pleted, EE_CS goes ow, EE_DO goes o high mpedance,
EE_DI stops latching in data, the last 16 data bits shifted
in are atched nto the 8502, and the serial shifting process
is halted. This process is repeated five more times, once
for each of the ive nternal MI registers as shown n Tables
10 and 11 and Figure 6. Once all six EE_CS access cycles
have been completed, then the EEI returns to the idle
state.
Table 10. EEI EE_CS Cycle Structure
<1>
START
<10>
OP[1:0]
<Register Addr.>
A[5:0]
<Data>
D[15:0]
000001
000011
000111
001111
011111
111111
Identification
MI Register 0
MI Register 1
MI Register 2
MI Register 3
MI Register 16
Symbol
Name
Definition
R/W
START
Start Bit
1 Read Out To EEPROM On Every EE_CS Cycle
R
OP[1:0]
EEPROM Opcode
Instruction
10 Read Out To EEPROM On Every EE_CS Cycle
R
A[5:0]
EEPROM
Register Address
EEPROM Register Address Where Data Will Be Fetched on
Each of the 6 EE_CS Cycles and Loaded into the MI Registers
as Shown in Table 10 And Figure 6.
R
D[15:0]
MI Data
These 16 Bits Contain Data Written from the External EEPROM
into the MI Registers According to Table 10. The First
Register Written from Regad = 000001 must Contain
A07d
16
for the Access to Continue.
W
START is Shifted Out First
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