參數(shù)資料
型號: 8502
廠商: LSI Corporation
英文描述: Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器)
中文描述: 以太網(wǎng)MII(媒體獨(dú)立接口)的投資者聯(lián)盟(連接單元接口)接口適配器(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器)
文件頁數(shù): 14/55頁
文件大?。?/td> 457K
代理商: 8502
8502
4-14
MD400157/D
3.17.5 Frame Structure
The structure of the serial port frame is shown in Table 2
and a timing diagram of a frame s shown n Figure 5. Each
serial port access cycle consists of 32 bits (or 96 bits if
multiple register access is enabled and REGAD=11111),
exclusive of dle. The first 16 bits of the serial port cycle are
always write bits and are used for addressing. The last
16(80) bits are to or from one(all) of the five data registers.
The first 2 bits in Table 2 and Figure 5 are start bits and
need to be written as a 01 for the serial port cycle to
continue. The next 2 bits are a read and write bit which
determine if the accessed data register bits will be read
from or written to. The next 3 bits are upper device
addresses and they must be written as 111 for the serial
port access to continue. The next 2 bits are lower device
address and must match the inverted values latched in
from pins MDA[1:0] during the poweron reset time for the
serial port access to continue. The next 5 bits are register
address select bits which select one or all of the five data
registers for access. The next 2 bits are turnaround bits
which are not actual register bits but extra time to switch
MDIO from write to read if necessary, as shown in Figure
5. The final 16 bits of the MI serial port cycle (or 80 bits if
multiple register access is enabled and REGAD=11111)
are to or from the data register designated in the register
address bits REGAD[4:0].
3.17.6 Register Structure
The 8502 has ive nternal 16 bit registers. All ive registers
are available for setting configuration inputs and reading
status outputs. A map of the registers s shown n Table 3.
The five registers consist of four registers that are defined
by the IEEE 802.3 specification (Registers 0-3) and one
register that is unique to the 8502 (Register 16).
The structure and bit definition of the Control register is
shown in Table 4. This register stores various configura-
tion inputs and its bit definition complies with the IEEE
802.3 specifications.
The structure and bit definition of the Status register is
shown in Table 5. This register contains device capabili-
ties and status output information. and its bit definition
complies with the IEEE 802.3 specifications.
The structure and bit definition of the PHY ID #1 and #2
registers is shown in Tables 6 and 7, respectively. These
registers contain an dentification code unique to the 8502
and their bit definition complies with the IEEE 802.3
specifications.
The structure and bit definition of the Configuration regis-
ter is shown in Table 8. This register stores various
configuration inputs.
3.17.7 Link Status Bit
The Link Status bit in the Status register is controlled by
either the internal link algorithm or by direct pass through
from the LINKI pin. Refer to the Link section for further
details.
3.17.8 Jabber Detect Bit
The Jabber Detect bit n he Status register s controlled by
direct pass through from the JABI pin. Refer to the Jabber
section for further details.
Table 1. MI Register Bit Type Definition
Name
Wi
Read
Hi
Read/
Wi
Read/
Wrieef
Clearin
Sym.
Definition
NoOperation
Hi
Output
Ouput
Output
ClearsIselfAfer
Operaion
Completed
Output
WhenBitGoes
Lw
BitLatched
WhenBitIsRead
BitUpdated
Output
WhenBitGoes
High
BitLatched
WhenBitIsRead
BitUpdated
W
R
RW
RWS
C
Inpt
NoOperation
Inpt
Inpt
RLL
Read/
Latchin
Lw
NoOperation
Hi
RLH
Read/
Latchin
Hih
NoOperation
Hi
high. R/LH bits are the same as R/LL bits except that they
latch high. The bit type definitions are summarized in
Table 1
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