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參數(shù)資料
| 型號： | 8502 |
| 廠商： | LSI Corporation |
| 英文描述： | Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器) |
| 中文描述： | 以太網(wǎng)MII（媒體獨(dú)立接口）的投資者聯(lián)盟（連接單元接口）接口適配器（以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器） |
| 文件頁數(shù)： | 11/55頁 |
| 文件大?。?/td> | 457K |
| 代理商： | 8502 |
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8502
4-11
MD400157/D
3.7 COLLISION
3.7.1 General
Collision is detected whenever the collision detect algo-
rithm senses a valid 10 MHz signal on the CI
±
collision
inputs. When collision is detected, the COL output is
asserted, CRS is asserted, and RX_DV is deasserted.
The collision function is disabled if the device is in the Full
Duplex mode or if the Link Status bit in the MI serial port
Status register is set to the Link Fail state.
3.7.2 Collision Detect Algorithm
The collision detect circuit looks for a valid 10 MHz signal
by monitoring the period of the waveform from the CI
±
inputs. If the period of the input waveform on CI
±
is
between 77-200 nS, he collision signal s considered o be
valid and collision is asserted. If the period of the input
waveform on CI
±
s ess than 48 nS or greater than 400 nS,
then collision s deasserted. Any high and ow pulse widths
less than 10 nS are rejected as noise.
3.7.3 Collision Indication
Collision detect can be programmed to appear on the
PLED1 pin by appropriately setting the programmable
LED output select bits in the MI serial port Configuration
register. When the PLED1 pin is programmed to be a
collision detect output, this pin is asserted low for 50 mS
every time a collision occurs. The PLED1 output is open
drain with resistor pullup and can drive an LED from VCC
or can drive another digital input.
3.7.4 Collision Test
The MII collision signal, COL, can be tested by setting the
collision test bit n the MI serial port Control register. When
this bit s set, TX_EN s ooped back onto COL and the AUI
trasmitter is forced to the idle state.
3.8 SOI (START OF IDLE)
The SOI pulse is a positive pulse inserted at the end of
every transmitted packet to indicate the end of data
transmission and the start of idle.
The AUI transmitter generates an SOI pulse at the end of
data transmission when TX_EN is deasserted. The
transmitted SOI output pulse meets the pulse template
requirements specified in IEEE 802.3 Section 7 and
shown in Figure 4.
The AUI receiver detects he SOI pulse by sensing missing
data transitions. Once the SOI pulse is detected, data
reception is ended and CRS is deasserted.
3.9 FULL DUPLEX MODE
Full Duplex mode allows transmission and reception to
occur simultaneously without a collision being signalled.
When Full Duplex mode is enabled, collision is disabled,
COL s deasserted regardless of the nput on CI
±
, and any
loopback of TX_EN to CRS is disabled, if enabled.
The device can be forced into the Full Duplex Mode by
setting the duplex bit in the MI serial port Control register.
3.10 LOOPBACK
Two different loopback modes are available on the 8502:
(1) TX_EN o CRS Loopback, and (2) diagnostic oopback.
TX_EN to CRS Loopback s enabled by setting the TX_EN
to CRS Loopback bit in the MI serial port Configuration
register. When this loopback mode is enabled, TX_EN is
looped back onto CRS during every transmit packet. This
TX_EN to CRS Loopback is disabled during collision,
when the device is placed in the Full Duplex mode, when
the Link Status bit in the MI serial port Status register is in
the Link Fail state, when he ransmit disable bit s set n he
MI serial port Configuration register, and any other condi-
tions where the transmitter is disabled.
A diagnostic loopback mode can also be selected by
setting the loopback bit in the MI serial port Control
register. When diagnostic loopback is enabled, TXD[3:0]
data is looped back onto RXD[3:0], TX_EN is looped back
onto CRS, RX_DV operates normally, and he AUI receive
and transmit paths are disabled.
Figure 4. AUI Transmit SOI Output Voltage Template
0
+V
dm
–V
dm
T
2
U
T
1
R
E
T = 200 ns Minimum
T = 8000 ns
U = –100 mV Maximum Undershoot
E = +/– 40 mV Max
R = <200 mV PK – PK
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