參數(shù)資料
型號(hào)： 8502
廠商： LSI Corporation
英文描述： Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器)
中文描述： 以太網(wǎng)MII（媒體獨(dú)立接口）的投資者聯(lián)盟（連接單元接口）接口適配器（以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器）
文件頁(yè)數(shù)： 12/55頁(yè)
文件大小： 457K
代理商： 8502
8502
4-12
MD400157/D
3.11 LINK
3.11.1 General
The status of the link is reported with the link status bit in
the MI serial port Status register. The Link Status bit (LINK
bit) can either be controlled by an internal link algorithm or
externally with the LINKI pin. The selection of the method
to set the LINK bit is determined by the LINKI pin. The
LINKI input pin is a three level pin. If LINKI=1 or 0, the 1
or 0 value is inverted and automatically passed through to
the LINK bit n he MI serial port Status register. If he LINKI
pin is left floating, the pin floats to VCC/2 and this level
indicates to the device that the internal link algorithm
should be used for setting the LINK bit.
3.11.2 Link Algorithm
The internal link algorithm is enabled by letting the LINKI
pin float. The internal link algorithm starts by setting the
LINK bit to the pass state when the device is powered up.
This bit stays n the pass state until a packet s transmitted.
When a packet is transmitted, the internal link algorithm
expects a corresponding receive packet to arrive at the
AUI inputs within 2
μ
S. If the expected receive packet
arrives within 2
μ
S after the start of a transmission, the
LINK bit stays in the Link Pass state. If the expected
receive packet doesn't arrive within 2
μ
S, then the LINK bit
goes to the Link Fail state. Since the LINK bit is an R/LL
bit (see section 3.18.4), it latches itself whenever it goes
low (Link Fail) and stays low until read out. Once it is read
out, then it returns high to the Link Pass state.
3.11.3 Link Indication
Link Detect can be programmed to appear on the PLED1
pin by appropriately setting he PLED configuration bit and
the programmable LED output select bits in the MI serial
port Configuration register. When the PLED1 pin is
programmed to be a link detect output, this pin is asserted
low whenever the device is in the Link Pass State. The
PLED1 output is open drain with resistor pullup and can
drive an LED from VCC or can drive another digital input.
3.12 JABBER
The Jabber Detect bit in the MI serial port Status register
is used to report the jabber condition. The 8502 does not
have a abber detect circuit, but the Jabber Detect bit (JAB
bit) can be controlled externally with the JABI pin. Thus, f
JABI =1 or 0, the 1 or 0 value is inverted and automatically
passed through to the JAB bit in the MI serial port Status
register.
3.13 RESET
The 8502 s reset when either VCC s applied to the device
or when the reset bit is set in the MI serial port Control
register. When reset bit is set to a 1, an internal power-
on reset pulse is generated which resets all internal
circuits, attempts to access an external EEPROM to load
the MI serial port bits, forces the MI serial port bits to either
their default values or to the contents of the external
EEPROM, and latches in the MI physical address values
on PLED[1:0]/MDA[1:0]. After the power-on reset pulse
has finished, the reset bit in the MI serial port Control
register s cleared to a 0 and the device s ready for normal
operation 500 mS after the reset was initiated.
3.14 POWERDOWN
The 8502 can be powered down by setting the powerdown
bit in the MI serial port Control register. In powerdown
mode, the AUI outputs are in high impedance state, all
functions are disabled except the MI serial port, and the
power consumption s reduced to ess than 10 mW. When
the device goes from powerdown to powerup state, the
device is ready for normal operation 500 mS after
powerdown was deaserted (powerdown bit cleared).
3.15 OSCILLATOR
The 8502 requires a 20 MHz reference frequency for
internal signal generation. This 20 MHz reference fre-
quency can be generated by either connecting an external
20 MHz crystal between OSCIN and GND or an external
20 MHz clock on OSCIN.
3.16 LED DRIVERS
The PLED[1:0] outputs are open drain with a resistor
pullup. These outputs can drive LED's tied to VCC.
The PLED[1:0] outputs can be individually programmed
through the MI serial port to do 4 different functions: (1)
Normal Function (2) On, (3) Off, and (4) Blink.
PLED[1:0] can be individually programmed by appropri-
ately setting the LED output select bits in the MI serial port
Configuration register. When PLED[1:0] are programmed
for their Normal function, these outputs indicate the spe-
cific functions described n the MI serial port Configuration
register shown on Table 9 (Collision, Activity, respec-
tively). When PLED[1:0] are programmed to be On, the
LED output drivers goes low, thus turning on the LED
under user control. When PLED[1:0] are programmed to
be Off, the LED output drivers will turn off, thus turning off
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