參數(shù)資料
型號(hào)： 8502
廠商： LSI Corporation
英文描述： Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器)
中文描述： 以太網(wǎng)MII（媒體獨(dú)立接口）的投資者聯(lián)盟（連接單元接口）接口適配器（以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器）
文件頁(yè)數(shù)： 24/55頁(yè)
文件大?。?/td> 457K
代理商： 8502
8502
4-24
MD400157/D
3.19 EXTERNAL EEPROM INTERFACE (EEI)
3.19.1 General
The default values of the MI serial port registers can be
modified externally through the External EEPROM Inter-
face, called EEI. The EEI will automatically fetch data
stored n an external EEPROM (or equivalent) and use his
data to overwrite the default values in the MI registers.
This automatic fetch and write function is initiated when
VCC is applied to the device or when the MI serial port
reset bit is set. The EEI can overwrite all the bits in the MI
registers including the read bits (with the exception of
RESET, JAB, and LINK).
The EEI is intended to interface to the 9346 family of
EEPROM's.
3.19.2 Signal Description
The EEI consists of four pins, EE_CS, EE_CLK, EE_DI,
and EE_DO. EE_CS is a chip select output. EE_CLK is a
serial shift clock output. EE_DI and EE_DO are the data
in and data out pins, respectively.
3.19.3 Frame Structure
Each EEI frame consists of six individual accesses of the
external EEPROM memory, called EE_CS cycles. A
diagram of the frame structure is shown in Figure 6.
Each EE_CS cycle (exclusive of the first cycle) accesses
one 16 bit register n the external EEPROM and moves the
contents of that EEPROM register into one of the five MI
registers. The correspondance of EE_CS cycle number to
which EEPROM register is read to which MI register is
written to is shown in Table 9 as well as Figure 6.
The first EE_CS cycle is used by the 8502 to determine if
there is an EEPROM or equivalent connected to the EEI;
it does not load any data into any MI register. This
identification of an EEPROM or equivalent on the EEI is
done by examination of a specific EEPROM register for a
specific data pattern. If the contents of the first EEPROM
register accessed (EEPROM register 000001) is A07D
,
then the remainder of the EEPROM data is fetched and
written nto the MI registers as described. If the content of
EEPROM register 000001 is not A07D
, the EEI frame is
terminated, the contents of the EEPROM are not written
into the MI registers, and the default values remain in the
MI registers.
Table 9. EEI To MI Register Correspondance
EE_CS
Cycle
EEI
MI Register Written To
Register
Read Out
(REG[5:0])
Address
Name
1
000001
-----
-----
2
000011
00000
Control
3
000111
00001
Status
4
001111
00010
PHY ID #1
5
011111
00011
PHY ID #2
6
111111
10000
Configuration
3.19.4 EE_CS Cycle Structure
A description of the EE_CS cycle structure is shown in
Table 10 and in Figure 6. Each EE_CS cycle consists of
25 bits. The first 9 bits of an EE_CS cycle are always read
bits and are used to provide instructions and register
addressing to the external EEPROM. The last 16 bits are
write bits and are loaded from the external EEPROM into
one of the MI registers per Table 9 and Figure 6.
The first bit in a EE_CS cycle is read out on the EEI as a
1 and instructs the external EEPROM to start an access
cycle. The next two bits are read out as a 10 and contain
the opcode instruction for the external EEPROM to
execute a read cycle. The next 6 bits are one of six register
addresses read out to the external EEPROM and contain
the address of the 16 bit register in the external EEPROM
where the data is to be fetched. On the same clock cycle
that the last register address bit is read out to the external
EEPROM, the external EEPROM may also send back a
"0" on EE_DO. The 8502 ignores this "0" data. The next
16 bits are written nto the 8502 from the EEPROM and are
written into a specific MI register as shown in Table 9 and
Figure 6.
There are three individual MI bits whose value will not be
modified or should not be modified through the EII: (1)
Reset, bit 0.15, (2) Link Detect, bit 1.2, and (3) Jabber
Detect, 1.1. The Reset bit should not be modified through
the EEI and should only be set to a 1 via a MI write to that
bit; the Link Detect and Jabber Detect bits will not be
modified by the EEI, so refer to the Link and Jabber
sections for more details how these bits are set and reset.
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