參數(shù)資料
型號: 8502
廠商: LSI Corporation
英文描述: Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨立于媒體接口與附屬單元接口適配器)
中文描述: 以太網(wǎng)MII(媒體獨立接口)的投資者聯(lián)盟(連接單元接口)接口適配器(以太網(wǎng)獨立于媒體接口與附屬單元接口適配器)
文件頁數(shù): 22/55頁
文件大?。?/td> 457K
代理商: 8502
8502
4-22
MD400157/D
Table 8. MI Register 16 (Configuration) Structure and Bit Definition
16.15
XMT_DIS
R/W
16.14
XMT_PDN
R/W
16.13
0
R/W
16.12
16.11
MREG
R/W
16.10
0
R/W
16.9
0
R/W
16.8
0
R/W
TXEN_CRS
R/W
16.7
16.6
16.5
16.4
16.3
16.2
0
R/W
16.1
0
R/W
16.0
0
R/W
PLED1_1
R/W or
R/WSC
PLED1_0
R/W or
R/WSC
PLED0_1
R/W or
R/WSC
PLED0_0
R/W or
R/WSC
PLED1_CFG
R/W
Bit
16.15
Symbol
XMT_DIS
Name
AUI Transmit
Disable
AUI Transmit
Powerdown
Definition
1 = AUI Transmitter Disabled, Force To Idle
0 = Normal
1 = AUI Transmitter Powered Down
0 = Normal
Reserved For Factory Use, Must Be 0
1 = TX_EN Looped Back To CRS While Non-Idle
0 = No Loopback
1 = Multiple Register Access Feature Enabled
0 = No Multiple Register Access
Reserved For Factory Use, Must Be 0
R/W
R/W
Def.
0
16.14
XMT_PDN
R/W
0
16.13
16.12
R/W
R/W
0
0
TXEN_CRS
TXEN To CRS
Loopback Enable
Multiple Register
Access Enable
16.11
MREG
R/W
0
16.10
16.9
16.8
16.7
16.6
R/W
0
0
0
1
1
PLED1_1
PLED1_0
Programmable
LED Output
Select, Pin
PLED1
11 = Collision
(PLED1 Is Low For
100 mS When Collision
Occurs,Then Pin
Returns High and Bit
Clears Itself)
R/W
or
R/W
SC
10 = LED Blink
(PLED1 Is Toggling 100 mS
Low, 100 mS High)
(PLED1 Is Low)
(PLED1 Is High)
(PLED0 Is Low For 100 mS
When Activity Occurs,Then
Pin Returns High and Bit
Clears Itself)
01 = LED On
00 = LED Off
11 = Activity
16.5
16.4
PLED0_1
PLED0_0
Programmable
LED Output
Select, Pin
PLED0
R/W
or
R/W
SC
1
1
10 = LED Blink
(PLED0 Is Toggling 100 mS
Low, 100 mS High)
(PLED0 Is Low)
(PLED0 Is High)
01 = LED On
00 = LED Off
1 = PLED1 Is Link Detect When PLED1_[1:0]=11
0 = PLED1 Is Collision When PLED1_[1:0]=11
16.3
PLED1_CFG
PLED1
Configuration
Select
R/W
0
16.2
16.1
16.0
Reserved For Factory Use, Must Be 0
Reserved For Factory Use, Must Be 0
Reserved For Factory Use, Must Be 0
x.15 Bit is Shifted First
R/W
R/W
R/W
0
0
0
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