參數(shù)資料
型號(hào)： 8502
英文描述： 8502 Ethernet MII to AUI Interface Adapter manual 7/97
中文描述： 8502以太網(wǎng)MII接口適配器的投資者聯(lián)盟手冊(cè)7 / 97
文件頁(yè)數(shù)： 7/55頁(yè)
文件大?。?/td> 457K
代理商： 8502
8502
4-7
7
MD400157/D
3.2 MEDIA INDEPENDENT INTERFACE (MII)
3.2.1 General
The Media Independent Interface, called MII, provides a
standardized interface between the 8502 and an external
Ethernet controller. The MII is a nibble wide packet data
interface defined in IEEE 802.3 specifications and shown
in Figure 2. The 8502 meets all the MII requirements
outlined in IEEE 802.3 specifications. The 8502 can
directly connect, without any external logic, to any Eth-
ernet controllers which also comply with the IEEE 802.3
MII specifications.
The MII consists of ourteen signals: four ransmit data bits
(TXD[3:0]), transmit clock (TX_CLK), transmit enable
(TX_EN), four receive data bits (RXD[3:0]), receive clock
(RX_CLK), carrier sense (CRS), receive data valid
(RX_DV), and collision (COL). The transmit and receive
clocks operate at 2.5 MHz.
On the transmit side, the TX_CLK output runs continu-
ously. When no data is to be transmitted, TX_EN input is
deasserted and any data on TXD[3:0] is ignored. When
TX_EN is asserted on rising edge of TX_CLK, data on
TXD[3:0] is clocked into the device on rising edges of the
TX_CLK. TXD[3:0] input data is actually nibble wide
packet data whose format needs to be the same as
specified n EEE 802.3 specifications and shown n Figure
2. When all the data on TXD[3:0] has been atched nto the
device, TX_EN is deasserted on rising edge of TX_CLK.
On he receive side, when nvalid data s sensed on he AUI
inputs, the receiver is idle. During idle, RX_CLK follows
TX_CLK, RXD[3:0] is held low, and CRS and RX_DV are
deasserted. When a valid packet is detected on the AUI
receive inputs, CRS is asserted and the clock recovery
process starts on the incoming data. After the receive
clock has been recovered from the data, the RX_CLK is
switched over to the recovered clock and the data valid
signal RX_DV is asserted on a falling edge of RX_CLK.
While RX_DV is asserted, valid data is clocked out of
3.0 Functional Description
3.1 GENERAL
The 8502 is a single chip interface IC's for connecting MII
to AUI. MII and AUI are acronyms or Media ndependent
Interface and Attachment Unit Interface, respectively.
Both of these interfaces are defined by IEEE 802.3 speci-
fications.
The 8502 has six main sections: Media Independent
Interface (MII), Manchester encoder, Manchester de-
coder, AUI transmitter, AUI receiver, and MI serial port.
On the transmit side, NRZ data s received on the MII from
an external Ethernet controller per the MII format de-
scribed in Figure 2. The NRZ data is then sent to the
Manchester encoder for formatting. The Manchester
encoded data s then sent to the AUI transmitter. The AUI
transmitter shapes the output and drives a 78 ohm AUI
cable. In addition, the transmitter generates start of idle
(SOI) pulses.
On the receive side, the AUI receiver receives incoming
Manchester encoded data from the AUI cable, removes
high requency noise rom he nput, determines f he nput
signal is a valid packet, and then converts the data from
AUI levels to internal digital levels. The AUI receiver also
detects start of dle (SOI) pulses and mplements a squelch
algorithm to reject invalid signals. The output of the AUI
receiver then goes to the Manchester decoder which
recovers a clock from the AUI data stream, recovers the
data, and converts the data back to NRZ. The NRZ data
is then transmitted to an external Ethernet controller
through the MII using the format shown in Figure 2.
The MI (Management Interface) serial port is a two pin
bidirectional port through which configuration inputs can
be set, and device capabilities and status outputs can be
read out.
A crystal oscillator generates a master clock or he device.
Each block plus the operating modes are described in
more detail in the following sections. A block diagram of
the 8502 is shown in Figure 1.
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PDF描述
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