參數(shù)資料
型號: 8502
英文描述: 8502 Ethernet MII to AUI Interface Adapter manual 7/97
中文描述: 8502以太網(wǎng)MII接口適配器的投資者聯(lián)盟手冊7 / 97
文件頁數(shù): 13/55頁
文件大小: 457K
代理商: 8502
8502
4-13
MD400157/D
the LED under user control. When PLED[1:0] are pro-
grammed to Blink, the LED output drivers will continuously
blink at a rate of 50 mS on, 50 mS off.
The default Normal functions for PLED1 and PLED0 are
Collision Detect and Activity, respectively. The Normal
function for PLED1 can be changed from Collision Detect
to Link Detect by setting the PLED1 Configuration Select
bit in the MI serial port Configuration register. When this
bit is set, the Normal function for PLED1 changes from
Collision to Link. That is, for PLED1 to be a Link Detect
output, the PLED1 Configuration Select and PLED1 Out-
put Select bits must all be high.
XMT_LED and RCV_LED outputs can drive LEDs to GND
indicating transmit and receive activity respectively. They
are asserted high for 50 mS every time a transmit or a
receive packet occurs.
3.17 MI SERIAL PORT
3.17.1 Signal Description
The MI serial port has four pins, MDC, MDIO, and
MDA[1:0]. MDC is the serial shift clock input. MDIO is a
bidirectional data I/O pin. MDA[1:0] are address pins for
the MI serial port.
MDA[1:0] inputs share the same pins as the PLED[1:0]
outputs, respectively. At powerup or reset, the PLED[1:0]
output drivers are high impedance for an interval towards
the end of the poweron reset time. During this nterval, the
values on these pins are latched into the device, inverted,
and used as the MI serial port addresses.
3.17.2 Timing
The MI serial port s dle when at east 32 continuous 1's are
detected on MDIO, and it remains idle as long as continu-
ous 1's are detected. During idle, MDIO is in the high
impedance state. When the MI serial port is in the idle
state, a 01 pattern on the MDIO pin initiates a serial shift
cycle. Data on MDIO s then shifted n on the next 14 rising
edges of MDC (MDIO is high impedance). If the multiple
register access mode is not enabled, on the next 16 rising
edges of MDC, data is either shifted in or out on MDIO,
depending on whether a write or read cycle was selected
with the bits READ and WRITE. After the 32 MDC cycles
have been completed, one complete register has been
read/written, the serial shift process is halted, data is
latched into the device, and MDIO goes into high imped-
ance state. Another serial shift cycle cannot be initiated
until the the idle condition (at least 32 continuous 1's) is
detected.
3.17.3 Multiple Register Access
Multiple registers can be accessed on a single MI serial
port access cycle with the multiple register access feature.
The multiple register access feature can be enabled by
setting the multiple register access enable bit in the MI
serial port Configuration register. When the multiple
register access feature is enabled, multiple registers can
be accessed on a single MI serial port access cycle by
setting the register address to 11111 during the first 16
MDC clock cycles. There is no actual register residing in
register address location 11111, so when the register
address s hen set o 11111, all ive registers are accessed
on the 80 rising edges of MDC that occur after the first 16
MDC clock cycles of the MI serial port access cycle. The
registers are accessed in numerical order from 0 to 16.
After all 96 MDC clocks have been completed, all the
registers have been read/written, the serial shift process s
halted, data s atched nto the device, and MDIO goes nto
high mpedance state. Another serial shift cycle cannot be
initiated until the the idle condition (at least 32 continuous
1's) is detected.
3.17.4 Bit Types
Since the serial port is bidirectional, there are many types
of bits. Write bits (W) are nputs during a write cycle and are
high impedance during a read cycle. Read bits (R) are
outputs during a read cycle and high impedance during a
write cycle. Read/Write bits (R/W) are actually write bits
which can be read out during a read cycle. R/WSC bits are
R/W bits that clear themselves after a set period of time or
after a specific event has completed. R/LL bits are read
bits that atch themselves when they go ow, and they stay
latched low until read. After they are read, they are reset
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