參數(shù)資料
型號(hào): 8502
英文描述: 8502 Ethernet MII to AUI Interface Adapter manual 7/97
中文描述: 8502以太網(wǎng)MII接口適配器的投資者聯(lián)盟手冊(cè)7 / 97
文件頁(yè)數(shù): 3/55頁(yè)
文件大?。?/td> 457K
代理商: 8502
8502
4-3
3
MD400157/D
Pin #
44L
8502
2
23
Pin Name
I/O
Description
VCC2
VCC1
Positive Supply.
+5 +/-5% Volts.
1
24
GND2
GND1
Ground.
0 Volts.
25
DO+
O
AUI Transmit Output, Positive.
26
DO-
O
AUI Transmit Output, Negative.
19
DI+
I
AUI Receive Input, Positive.
20
DI-
I
AUI Receive Input, Negative.
21
CI+
I
AUI Collision Input, Positive.
22
CI-
I
AUI Collision Input, Negative.
28
RBIAS
Internal Bias Current Set.
An external resistor connected between
this pin and GND will create a reference current for the internal
bias circuits.
43
OSCIN
I
Clock Oscillator Input.
There must be either a 20 MHz crystal or a
20 MHz clock tied between this pin and GND. TX_CLK output clock
is generated from this input.
30
TX_CLK
O
Transmit Clock Output.
This Media Independent Interface output
provides a clock to the controller. Transmit data from the controller
on TXD and TX_EN is clocked in on rising edges of TX_CLK and
OSCIN.
40
TX_EN
I
Transmit Enable Input.
This Media Independent Interface input has
to be asserted active high to indicate that data on TXD is valid and
is clocked in on rising edges of TX_CLK and OSCIN.
34
33
32
31
TXD3
TXD2
TXD1
TXD0
I
Transmit Data Input.
These Media Independent Interface inputs contain
input nibble data to be transmitted on the AUI outputs and are clocked in
on rising edges of TX_CLK and OSCIN.
13
RX_CLK
O
Receive Clock Output.
This Media Independent Interface output
provides a clock to the controller. Receive data on RXD and RX_DV
is clocked out to the controller on falling edges of RX_CLK.
15
CRS
O
Carrier Sense Output.
This Media Independent Interface output is
asserted when valid data is detected on the AUI inputs
and is clocked out on falling edges of RX_CLK.
14
RX_DV
O
Receive Data Valid Output.
This Media Independent Interface output is
asserted active high when valid decoded data is present on the RXD
outputs and is clocked out on falling edges of RX_CLK.
3
6
7
8
RXD3
RXD2
RXD1
RXD0
O
Receive Data Output.
These Media Independent Interface outputs
contain receive nibble data from the AUI input and are clocked out on
falling edges of RX_CLK.
1.0 Pin Description
相關(guān)PDF資料
PDF描述
8502 Ethernet MII(Media Independent Interface) to AUI(Attachment Unit Interface) Interface Adapter(以太網(wǎng)獨(dú)立于媒體接口與附屬單元接口適配器)
8504 Analog Miscellaneous
8503 Analog Miscellaneous
8506301YX 16-Bit Microcontroller
8506301ZX 16-Bit Microcontroller
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