
8502
4-53
MD400157/D
Page 10, Section 3.7.3 Receive Activity Indication; reference to 100 mS has been changed to 50 mS.
- New paragraph two copy; RCV_LED is receive activity output during normal operation. This pin is asserted high
for 50 mS every time a receive packet occurs. The RCV_LED output can drive an LED to GND or can drive
another digital input.
- Paragraph three copy has been changed from ...The PLED0 pin is only available on the 8502 (44L)... to ...The
PLED0 and RCV_LED pins are only available on the 8502 (44L).
Page 11, Section 3.8.3 Collision Indication
- Reference to 100 mS has been changed to 50 mS.
Page 12, - Section 3.15 POWERDOWN; Reference to 0.5 mW has been changed to 10 mW.
- Section 3.17 LED DRIVERS; Paragraph 3, reference to 100 mS have been changed to 50 mS.
- New paragraph; XMT_LED and RCV_LED outputs can drive LEDs... has been added.
Page 13, Section 3.18.1 Signal Description second paragraph; copy has change from ...PLED[1:0] output drivers are
high impedance for an interval called the poweron reset time. During the poweron reset interval... to ...PLED[1:0]
output drivers are high impedance for an interval towards the end of the poweron reset time. During this interval,
Page 14, Section 3.18.5 Frame Structure, copy change, first paragraph; copy has been change from...The last 16/80 bits
are from one/all of the five data registers... to ...The last 16(80) bits are to or from one(all) of the five data registers.
- Second paragraph, copy has been change from ...accessed data register bits will be read or write. The next 3
bits are upper device ... to ... accessed data register bits will be read from or written to. The next 3 bits are upper
device...
- Second paragraph, copy has been change from ... The next 5 bits are register address select bits which select
one of the five data registers for access ... to ... The next 5 bits are register address select bits which select one
or all of the five data registers for access....
- Second paragraph, copy has been change from ... cycle (or 80 bits if multiple register access is enabled and
REGAD=11111) come from the data register ... to ... cycle (or 80 bits if multiple register access is enabled and
REGAD=11111) are to or from the data register ...
- Table 2. MI Register Bit Type Definition, R/WS C Definition; Clears Itself After Operation Completed, has been
moved from Write Cycle to Read Cycle.
Page 15, Figure 5. MI Serial Port Frame Timing Diagram
- References to ST, OP, PHYAD, REGAD, TA, DATA have been changed to ST[1:0], OP[1:0], PHYAD[4:0],
REGAD[4:0], TA[1:0], DATA[15:0]
Page 27, Figure 8. External MII -AUI Schematics Using 8502 with EEPROM and LED's
- References to EE/DO and EE_CLK have been changed to EE_DO/RCV_LED and EE_CLK/XMT_LED.
- 1K Resisters and LEDs have been added to EE_DO/RCV_LED and EE_CLK/XMT_LED.
Page 36, DC Electrical Characteristics
- IIL Conditions MDA[1:0] has been changed to VIN = GND MDA[1:0].
- IIL Conditions OSCIN LINKI has beeen changed to VIN = GND OSCIN LINKI.
- VOH Limit (Min) has been changed from 4 to VCC - 1.0.
- VOH Conditions, XMT_LED, RCV_LED have been added.
- New VOH Row, Limit (MIN) = VCC -1.0, Limit (UNIT) = Volt, Conditions IOH = 10
μ
A XMT_LED, RCV_LED has
been added.
- ICC Transmitting Limit (Typ) is now 85.
- ICC Transmitting Limit (Max) has been changed from 85 to 110.
- ICC Powerdown Mode Limit (Typ) is now 1.3.
- ICC Powerdown Mode Limit (Max) is now 3.06.
Page 38, AUI Characteristics Receive
- ROCV Limit (TYP) has changed from V
CC
/2
±
0.5 to 3.0
±
0.5.
- RCMR Limit (TYP) has changed from V
CC
/2
±
1.0 to ROVC
±
0.5
Page 39, Figure 13. 20 MHz Clock Timing
- TX_CLK Timing has been changed.
20 MHz Clock Timing Characteristics
- t
4
Limit (Max) has been changed from 10 to 20.
Revision History