參數(shù)資料
型號: 8502
英文描述: 8502 Ethernet MII to AUI Interface Adapter manual 7/97
中文描述: 8502以太網(wǎng)MII接口適配器的投資者聯(lián)盟手冊7 / 97
文件頁數(shù): 32/55頁
文件大小: 457K
代理商: 8502
8502
4-32
MD400157/D
4.5 MI SERIAL PORT
4.5.1 General
The 8502 has a MI serial port to set all of the devices's
configuration inputs and read out the status outputs. Any
external device that has a IEEE 802.3 compliant MI inter-
face can connect directly to the 8502 without any glue
logic, as shown in Figures 7-10.
As described earlier, the MI serial port consists of 4 lines:
MDC, MDIO, and MDA[1:0]. However, only 2 lines, MDC
and MDIO, are needed to shift data in and out. MDA[1:0]
are provided for convenience only.
The MDA[1:0] addresses are inverted inside the 8502
before going to the MI serial port block. For example, the
MDA[1:0] pins would have to be pin strapped to 11 exter-
nally in order to successfully match the MI physical ad-
dress bits PHYAD[1:0]=00 internally.
4.5.2 Multiple Register Access
If the MI serial port needs to be constantly polled in order
to monitor changes in status output bits, all registers can
be accessed on a single MI serial port access cycle by
setting the register address REGAD[4:0]=11111 with the
multiple register access mode enabled. This eliminates
the need to poll registers individually. Multiple register
access is normally disabled but can be enabled by setting
the multiple register access bit n he MI serial port Configu-
ration register.
4.5.3 Serial Port Addressing
The device address for the MI serial port is selected by
tying the MDA[1:0] pins to the desired value. MDA[1:0]
share the same pins as the PLED[1:0] outputs, respec-
tively, as shown in Figure 12a. At powerup or reset, the
output drivers are high mpedance or an nterval called he
poweron reset ime. During he power on reset nterval, he
value on hese pins s atched nto he device, nverted, and
used as the MI serial port address. The LED outputs are
open drain with internal resistor pullup to VCC.
If an LED is desired on the LED outputs, then an LED and
resistor are tied to VCC as shown in Figures 12b. If a high
address is desired, then the LED to VCC automatically
makes the latched address value a high. If a low value for
the address s desired, then a 50K resistor to GND must be
added as shown in Figure 12b.
If no LED's are needed on the LED outputs, the selection
of addresses can be done without any external compo-
nents as shown n Figure 12c. If a high address s desired,
the pin should be eft loating and he nternal pullup will pull
the pin high during power on reset and latch in a high
address value. If a ow address s desired, then the output
pin should be tied to GND or tied to GND through an
optional 10K resistor as shown n Figure 12c. The optional
10K resistor allows the pin to be used as a digital output
under normal conditions.
4.6 RESET
The reset function n the 8502 resets all the nternal timers,
sets all the input configuration bits in the MI serial port to
their default values, loads data nto he MI from an external
EEPROM (if connected), and latches in the physical ad-
dress values for the serial port on MDA[1:0]. Reset can be
initiated internally or externally.
An internal reset automatically occurs when VCC is
applied to the 8502 or when the device comes out of the
powerdown state.
An external reset can be initiated by setting the reset bit in
the serial port Control register. Setting this bit will create
a reset and this bit will clear itself automatically when the
reset is completed.
It is not necessary to use the reset function in normal
operation; it is available if external control of reset is
desired.
4.7 EXTERNAL EEPROM
The EEI s ntended as an nexpensive and convenient way
to override the MI serial port default values with a user
defined set. The EEI provides a glueless interface to the
industry standard 9346 EEPROM. The 8502 can auto-
matically detect whether an external EEPROM is present,
so no configuration s necessary. The schematic n Figure
8 shows how an external 9346 EEPROM can be con-
nected directly to the 8502. A device other than the 9346
can be connected to the EEI provided it complies with the
timing and frame structure of the EEI.
One unique feature of the EEI is that it can modify the
default values of he read bits n he MI. Normally, when he
read bits are accessed through the MI, they can only be
read out and cannot be written nto. When the read bits are
accessed through the EEI, however, they become write
bits and can be overwritten by the contents of the
EEPROM. This feature allows the user to modify the OUI
and other capability bits to match the characteristics of the
end equipment, not the 8502 itself.
If an external EEPROM or other device s used with he EEI
to override the MI register default values, the EEPROM
needs to be programmed according to the EEPROM
memory map shown in Table 14. In Table 14, the names
for individual bit locations correspond to the MI register bit
names, and values in these register locations in the
EEPROM will be automatically loaded into the corre-
sponding MI bit locations when a reset is initiated.
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