參數(shù)資料
型號(hào): 84225
廠商: LSI Corporation
英文描述: Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device (Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications)(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器))
中文描述: 四100BaseTX/100BaseFX/10BaseT物理層裝置(高度集成的以太網(wǎng)收發(fā)器,雙絞線和光纖以太網(wǎng)的應(yīng)用)(四通道100BaseTX/100BaseFX/10BaseT物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器) )
文件頁(yè)數(shù): 6/86頁(yè)
文件大?。?/td> 1297K
代理商: 84225
6
MD400183/A
84225
1.0 PIN DESCRIPTION (cont’d)
Management Interface (MI)
Pin #
Pin Name
I/O
Description
99
MDC
I
Management Interface (MI) Clock Input.
into and out of MDIO on rising edges.
This MI clock shifts serial data
97
MDIO
I/O
Management Interface (MI) Data Input/Output.
contains serial data that is clocked in and out on rising edges of the MDC
clock.
This bidirectional pin
98
REGDEF
I
Pullup
Invalid Register Read Select
This active low input controls the default values that are read from invalid
(unused) register locations.
1 = All unused register locations will return a value of ‘0000’ when read.
0 = All unused register locations will return a value of ‘ffff’ when read.
Note: Not available on Rev. B product. On Rev. B product all invalid register
locations return a value of ‘0000’ when read.
20
19
18
PHYAD[4:2]
I
MI Physical Device Address Input.
significant bits of the PHY address.
These pins set the three most
The two least significant bits of the PHY address are set internally to match
the channel number, as shown below:
PHYAD1 PHYAD0
Channel 3 1 1
Channel 2 1 0
Channel 1 0 1
Channel 0 0 0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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8422-51 制造商:ASM-SENSOR 制造商全稱:ASM GmbH 功能描述:MEMORY HiLOGGER
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