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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 22/86頁 |
| 文件大小： | 1297K |
| 代理商： | 84225 |
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MD400183/A
84225
In the unsquelch state, the receive threshold level is
reduced by approximately 30% for noise immunity reasons
and is called the unsquelch level. When the receiver is in
the unsquelch state the input signal is considered valid.
The device stays in the unsquelch state until loss of data is
detected. Loss of data is detected if no alternating polarity
unsquelch transitions are detected during any 10 uS
interval. When the loss of data is detected, the receive
squelch level is re-established.
2.9.4 Squelch - 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical to
the 100 Mbps mode, except:
The 10 Mbps squelch algorithm is not used for link
integrity, but to sense the beginning of a packet.
The receiver goes into the unsquelch state if the input
voltage exceeds the squelch levels for three bit times
with alternating polarity within a 50-250 nS interval.
The receiver goes into the squelch state when SOI is
detected.
Unsquelch detection has no affect on link integrity, link
pulses are used for that in 10 Mbps mode.
Start of packet is determined when the receiver goes
into the unsquelch state and CRS is asserted.
The receiver meets the squelch requirements defined in
IEEE 802.3 Clause 14.
2.9.5 Receive Level Adjust
The receiver squelch and unsquelch levels can be lowered
by 4.5 dB by setting the receive level adjust bit in the MI
serial port Channel Configuration register. By setting this
bit, the device can support cable lengths exceeding
100 meters.
2.10 FIBER INTERFACE
2.10.1 General
The Fiber Interface implements the 100BaseFX function
defined in IEEE 802.3.
The Fiber Interface consists of three signals: (1) a
differential PECL data output (FXOP/FXON), (2) a
differential PECL data input (FXIP/FXIN), and (3) a PECL
signal detect (SD/FXEN).
The Fiber Interface section consists of four blocks: (1)
transmitter, (2) receiver, (3) signal detect, and (4) far end
fault.
The Fiber Interface can be independently selected for
each channel with the SD/FXEN_[3:0] pins.
The Fiber Interface is disabled in 10Mbps mode.
Autonegotiation and the scrambler/descrambler are
disabled when the Fiber Interface is enabled.
The Fiber Interface meets all IEEE 802.3 requirements.
2.10.2 Transmitter
The FX transmitter converts data from the 4B5B encoder
into binary NRZI data and outputs the data onto the
FXOP/FXON pins for each channel. The output driver is a
differential current source that will drive a 100 ohm load to
ECL levels. The FXOP/FXON pins can directly drive an
external fiber optic transceiver. The FX transmitter meets
all the requirements defined in IEEE 802.3.
The FX transmit output current level is derived from an
internal reference voltage and the external resistor on
REXT pin.
2.10.3 Receiver
The FX receiver (1) converts the differential ECL inputs on
the FXIP/FXIN pins for each channel to a digital bit
stream, (2) validates the data on FXIP/FXIN with the SD/
FXEN input pin for each channel, and (3) enable/disables
the Fiber Interface with the SD/FXEN pin for each
channel. The FX receiver meets all requirements defined
in IEEE 802.3.
The input to the FXIP/FXIN pins can be directly driven
from a fiber optic transceiver and first goes to a
comparator. The comparator compares the input
waveform against the internal ECL threshold levels to
produce a low jitter serial bit stream with internal logic
levels. The data from the comparator output is then
passed to the clock and data recovery block provided the
signal detect input, SD/FXEN, is asserted. The signal
detect function is described in the next section.
2.10.4 Signal Detect
The FX receiver has a signal detect input pin, SD/FXEN,
for each channel which indicates whether the incoming
data on FXIP/FXIN is valid or not for that channel. The
SD/FXEN pin can be driven directly from an external fiber
optic transceiver and meets all requirements defined in
the IEEE 802.3 specifications.
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