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參數(shù)資料
| 型號： | 84225 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 5/86頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | 84225 |
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MD400183/A
5
84225
1.0 PIN DESCRIPTION (cont’d)
Controller Interface (MII & RMII)
Pin #
Pin Name
I/O
Description
87
69
50
31
TXCLK_[3:0]
O
Transmit Clock Output.
controllers. Transmit data from the controller on TXD, TXEN, and TXER is
clocked in on the rising edges of TXCLK and CLKIN.
These interface outputs provide clocks to external
88
70
51
32
TXEN_[3:0]
I
Transmit Enable Input.
high to allow data on TXD and TXER to be clocked in on the rising edges of
TXCLK and CLKIN.
These interface inputs must be be asserted active
[92:89]
[74:71]
[55:52]
[36:33]
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
I
Transmit Data Input.
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK and CLKIN. In RMII mode, only TXD[1:0] are used.
These interface inputs contain input nibble data to be
86
68
49
30
TXER_[3:0]/
TXD4_[3:0]
I
Transmit Error Input.
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK when TXEN is asserted.
These interface inputs initiate an error pattern to be
If the channel is placed in the Bypass 4B5B Encoder mode, these pins are
reconfigured to be the fifth TXD transmit data input, TXD4. In RMII mode,
these pins are not used.
84
66
47
28
RXCLK_[3:0]
O
Receive Clock Output.
controller. Receive data on RXD, RXDV, and RXER is clocked out to the
controller on falling edges of RXCLK.
These interface outputs provide a clock to the
94
76
58
38
CRS_[3:0]
O
Carrier Sense Output.
when valid data is detected on the receive TP or FX inputs and is clocked
out on the falling edge of RXCLK.
These interface outputs are asserted active high
83
65
46
27
RXDV_[3:0]
O
Receive Data Valid Output.
high when valid decoded data is present on the RXD outputs and is clocked
out on falling edges of RXCLK. In RMII mode, these pins are not used.
These interface outputs are asserted active
[79:82]
[61:64]
[42:45]
[23:26]
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
O
Receive Data Output.
data from the TP or FX inputs and are clocked out on the falling edges of
RXCLK. In RMII mode, only RXD[1:0] are used.
These interface outputs contain recovered nibble
85
67
48
29
RXER_[3:0]/
RXD4_[3:0]
O
Receive Error Output.
when coding or other specified errors are detected on the TP or FX inputs
and are clocked out on falling edges of RXCLK.
These interface outputs are asserted active high
If the channel is placed in the Bypass 4B5B Decoder mode, these pins are
reconfigured to be the fifth RXD receive data output, RXD4.
93
75
57
37
COL_[3:0]
O
Collision Output.
collision between transmit and receive data is detected.
These interface outputs are asserted active high when
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