參數(shù)資料
型號: 82562G
廠商: Intel Corp.
英文描述: Mbps Platform LAN Connect
中文描述: Mbps的平臺局域網(wǎng)連接
文件頁數(shù): 33/44頁
文件大小: 503K
代理商: 82562G
Networking Silicon — 82562G
Datasheet
29
7.0
82562G Test Port Functionality
The 82562G’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the
device. The port provides the ability to perform basic production level testing.
7.1
Asynchronous Test Mode
An asynchronous test mode is supported for system level design use. The modes are selected
through the use of the Test Port input pins (TESTEN, ISOL_TCK, ISOL_TI and ISOL_EXEC) in
static combinations. During normal operation the test pins must be pulled down through a resistor
(pulling Test high enables the test mode). All other port inputs may have a pull-down at the
designers discretion.
7.2
Test Function Description
The 82562G TAP mode supports several tests that can be used in board level design. These tests
can help verify basic functionality and test the integrity of solder connections on the board. The
tests are described in the following sections.
The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the
placement of the 82562G to be validated at board test. The XOR Tree was chosen for its speed
advantages. Modern Automated Test Equipment (ATE) can perform a complete peripheral scan
without support at the board level. This command connects all output signals of the input buffers in
the device periphery into an XOR Tree scheme. All output drivers of the output-buffers, except the
test output (TOUT) pin, are put into high-Z mode. These pins are driven to affect the tree’s output.
Any hard strapped pins will prevent the tester from scanning correctly. The XOR Tree test mode is
obtained by placing the test pins in the following configuration (refer to
Table 7
):
TESTEN = 1
ISOL_TCK = 0
ISOL_TI = 0
ISOL_EXEC = 0.
Table 7. XOR Tree Chain Order
Chain Order
Chain
1
JTXD2
2
JTXD1
3
JTXD0
4
JRSTSYNC
5
ADV10 (LAN_DISABLE#)
6
JCLK
7
JRXD2
8
JRXD1
9
JRXD0
10
ACTLED#
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