- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378216 > 82562G (Intel Corp.) Mbps Platform LAN Connect PDF資料下載
參數(shù)資料
| 型號： | 82562G |
| 廠商： | Intel Corp. |
| 英文描述： | Mbps Platform LAN Connect |
| 中文描述： | Mbps的平臺局域網(wǎng)連接 |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 82562G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Networking Silicon — 82562G
Datasheet
15
5.1.1.4
Transmit Driver
The transmit differential lines are implemented with a digital slope controlled current driver that
meets Twisted Pair Physical Media Device (TP-PMD) specifications. Current is sunk from the
isolation transformer by the transmit differential pins. The conceptual transmit differential
waveform for 100 Mbps is illustrated in the following figure.
Figure 3. Conceptual Transmit Differential Waveform
The magnetics module external to the 82562G converts I
TDP
and I
TDN
to 2.0 V
PP
, as required by
the TP-PMD specification. The same magnetics used for 100BASE-TX mode can also work in
10BASE-T mode.
5.1.2
100BASE-TX Receive Blocks
The receive subsection of the 82562G accepts 100BASE-TX MLT-3 data on the receive differential
pair. Due to the advanced digital signal processing design techniques employed, the 82562G will
accurately receive valid data from Category 5 (CAT5) UTP and Type 1 STP cable of length well in
excess of 100 meters.
5.1.2.1
Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the shape of the received signal, equalizing the signal to meet
superior data dependent jitter performance.
5.1.2.2
Receive Clock and Data Recovery
The clock recovery circuit uses advanced digital signal processing technology to compensate for
various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data
to the MLT-3 decoder.
5.1.2.3
MLT-3 Decoder, Descrambler, and Receive Digital Section
The 82562G first decodes the MLT-3 data, and then the descrambler reproduces the 5B symbols
originated in the transmitter. The descrambling is based on synchronization to the transmission of
the 11-bit Linear Feedback Shift Register (LFSR) during an idle phase. The data is decoded at the
4B/5B decoder. After the 4B symbols are obtained, the 82562G outputs the receive data to the
CSMA unit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8256AH | MULTIFUNTION MICROPROCESSOR SUPPORT CONTROLLER |
| 82571EB | Gigabit Ethernet Controller |
| 82572EI | Gigabit Ethernet Controller |
| 8257 | PROGRAMMABLE DMA CONTROLLER |
| 82586 | IEEE802.3 ETHERNET LAN COPROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82562GT | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:10/100 Mbps Platform LAN Connect (PLC) |
| 82562GZ | 制造商:Intel 功能描述: |
| 82562V | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:10/100 Mbps Platform LAN Connect |
| 82-56-302-60 | 制造商:Southco 功能描述: |
| 82563EB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel?? 82563EB/82564EB Gigabit Ethernet Controllers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。