參數(shù)資料
型號： 82562G
廠商： Intel Corp.
英文描述： Mbps Platform LAN Connect
中文描述： Mbps的平臺局域網(wǎng)連接
文件頁數(shù)： 3/44頁
文件大?。?/td> 503K
代理商： 82562G
Datasheet
i
82562G — Networking Silicon
Contents
1.0
Introduction.........................................................................................................................1
Overview......................................................................................................................1
References...................................................................................................................1
Product Codes .............................................................................................................1
1.1
1.2
1.3
2.0
82562G Architectural Overview..........................................................................................3
LAN Connect Interface.................................................................................................3
Reset/Synchronize Operations..............................................................................4
Reset Considerations ............................................................................................4
LAN Connect Clock Operations.............................................................................5
Hardware Configuration ...............................................................................................5
2.1
2.1.1
2.1.2
2.1.3
2.2
3.0
Performance Enhancements..............................................................................................7
New Usage Modes: 1, 2, 3, and 4................................................................................7
Pin Usage for Modes 1, 2, 3, and 4.......................................................................7
Enhanced Tx Mode................................................................................................8
3.1
3.1.1
3.1.2
4.0
82562G Signal Descriptions...............................................................................................9
Signal Type Definitions ...............................................................................................9
Twisted Pair Ethernet (TPE) Pins ...............................................................................9
External Bias Pins .......................................................................................................9
Clock Pins .................................................................................................................10
Platform LAN Connect Interface Pins .......................................................................10
LED Pins ...................................................................................................................11
Miscellaneous Control Pins .......................................................................................11
Power and Ground Connections ...............................................................................12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.0
Physical Layer Interface Functionality..............................................................................13
100BASE-TX Mode....................................................................................................13
100BASE-TX Transmit Blocks.............................................................................13
100BASE-TX Receive Blocks..............................................................................15
10BASE-T Mode ........................................................................................................16
10BASE-T Transmit Blocks.................................................................................16
10BASE-T Receive Blocks..................................................................................16
Analog References.....................................................................................................17
Dynamic Reduced Power & Auto Plugging Detection................................................17
Auto Plugging Detection......................................................................................18
Dynamic Reduced Power....................................................................................18
Configuration .......................................................................................................18
5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.3
5.4
5.4.1
5.4.2
5.4.3
6.0
Platform LAN Connect Registers .....................................................................................19
Medium Dependent Interface (MDI) Registers 0 through 7 .......................................19
Register 0: Control Register Bit Definitions ........................................................19
Register 1: Status Register Bit Definitions ..........................................................20
Register 2: PHY Identifier Register Bit Definitions ..............................................21
Register 3: PHY Identifier Register Bit Definitions ..............................................21
Register 4: Auto-Negotiation Advertisement Register Bit Definitions .................21
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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