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參數(shù)資料
| 型號： | 82562G |
| 廠商： | Intel Corp. |
| 英文描述： | Mbps Platform LAN Connect |
| 中文描述： | Mbps的平臺(tái)局域網(wǎng)連接 |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 82562G |
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82562G — Networking Silicon
16
Datasheet
In 100BASE-TX mode, the 82562G can detect errors in receive data in a number of ways. Any of
the following conditions is considered an error:
Link integrity fails in the middle of frame reception.
The start of stream delimiter “JK” symbol is not fully detected after idle.
An invalid symbol is detected at the 4B/5B decoder.
Idle is detected in the middle of a frame (before “TR” is detected).
5.2
10BASE-T Mode
5.2.1
10BASE-T Transmit Blocks
5.2.1.1
10BASE-T Manchester Encoder
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock
performs the Manchester encoding. The Manchester code always has a mid-bit transition. The
boundary transition occurs only when the data is the same from bit to bit. For example, if the value
is 11b, then the change is from low to high within the boundary.
5.2.1.2
10BASE-T Driver and Filter
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. The 82562G supports both technologies through one pair of transmit differential
pins and by externally sharing the same magnetics.
In 10 Mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line
drivers reduce their drive level during the second half of “wide” (100 ns) Manchester pulses and
maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. This
reduces line overcharging during wide pulses, a major source of jitter.
5.2.2
10BASE-T Receive Blocks
5.2.2.1
10BASE-T Manchester Decoder
The 82562G performs Manchester decoding and timing recovery in 10BASE-T mode. The
Manchester encoded data stream is decoded from the receive differential pair. This data is
transferred to the controller at 2.5 MHz/nibble. The high-performance circuitry of the 82562G
exceeds the IEEE 802.3 jitter requirements.
5.2.2.2
10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter
In 10 Mbps mode, data is expected to be received on the receive differential pair after passing
through isolation transformers. The filter is implemented inside the 82562G for supporting single
magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the
Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive
buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the
requirements of the 10BASE-T standard.
The following line activity is determined to be inactive and is rejected as invalid data:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82562GT | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:10/100 Mbps Platform LAN Connect (PLC) |
| 82562GZ | 制造商:Intel 功能描述: |
| 82562V | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:10/100 Mbps Platform LAN Connect |
| 82-56-302-60 | 制造商:Southco 功能描述: |
| 82563EB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel?? 82563EB/82564EB Gigabit Ethernet Controllers |
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