- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369345 > 7782 (意法半導體) 32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory PDF資料下載
參數(shù)資料
| 型號： | 7782 |
| 廠商： | 意法半導體 |
| 英文描述： | 32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory |
| 中文描述： | 32兆位（含2Mb × 16，雙行，突發(fā)）1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 20/63頁 |
| 文件大?。?/td> | 435K |
| 代理商： | 7782 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁
M58CR032C, M58CR032D
20/63
gram/Erase Controller does it automatically before
erasing.
Two Bus Write cycles are required to issue the
command.
I
The first bus cycle sets up the Erase command.
I
The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts. Erase aborts if Reset turns
to V
IL
. As data integrity cannot be guaranteed
when the Erase operation is aborted, the block
must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register until a
Read command is issued.
During Erase operations the bank containing the
block being erased will only accept the Read Sta-
tus Register command and the Program/Erase
Suspend command, all other commands will be ig-
nored. Typical Erase times are given in Table 12,
Program, Erase Times and Program/Erase Endur-
ance Cycles.
See Appendix B, Figure 22, Block Erase Flowchart
and Pseudo Code, for a suggested flowchart for
using the Block Erase command.
Bank Erase Command
The Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
’1’. All previous data in the bank is lost. The Bank
Erase command will ignore any protected blocks
within the bank. If the bank is protected then the
Erase operation will abort, the data in the bank will
not be changed and the Status Register will output
the error.
Two Bus Write cycles are required to issue the
command.
I
The first bus cycle sets up the Bank Erase
command.
I
The second latches the bank address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Bank Erase
Confirm (D0h), Status Register bits b4 and b5 are
set and the command aborts. Erase aborts if Re-
set turns to V
IL
. As data integrity cannot be guar-
anteed when the Erase operation is aborted, the
bank must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register until a
Read command is issued.
During Erase operations the bank being erased
will only accept the Read Status Register com-
mand and the Program/Erase Suspend command,
all other commands will be ignored. Typical Erase
times are given in Table 12, Program, Erase
Times and Program/Erase Endurance Cycles.
Program Command
The memory array can be programmed word-by-
word. Only one bank can be programmed at any
one time. The other bank must be in Read mode
or Erase Suspend. Two bus write cycles are re-
quired to issue the Program Command.
I
The first bus cycle sets up the Program
command.
I
The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
After programming has started, Read operations
in the bank being programmed output the Status
Register content.
During Program operations the bank being pro-
grammed will only accept the Read Status Regis-
ter command and the Program/Erase Suspend
command. Typical Program times are given in Ta-
ble 12, Program, Erase Times and Program/Erase
Endurance Cycles.
Programming aborts if Reset goes to V
IL
. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix B, Figure 18, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. The two words must differ only for the
address A0. Only one bank can be programmed at
any one time. The other bank must be in Read
mode or Erase Suspend.
Programming should not be attempted when V
PP
is not at V
PPH
. The command can be executed if
V
PP
is below V
PPH
but the result is not guaranteed.
Three bus write cycles are necessary to issue the
Double Word Program command.
I
The first bus cycle sets up the Double Word
Program Command.
I
The second bus cycle latches the Address and
the Data of the first word to be written.
I
The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 7801-301XC | HIGH SPEED, BUFFER AMPLIFIER AMP |
| 78042FG | 1 watt dc-dc converters |
| 78044F | Common to 78K/0 Series |
| 780058 | Common to 78K/0 Series |
| 780058Y | Common to 78K/0 Series |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 778200-01 | 制造商:NI 制造商全稱:National Instruments Corporation 功能描述:4-Channel Monochrome Image Acquisition |
| 778201-01 | 制造商:NI 制造商全稱:National Instruments Corporation 功能描述:Real-Time Embedded Controllers for PXI |
| 778204-01 | 制造商:NI 制造商全稱:National Instruments Corporation 功能描述:S Series Multifunction DAQ 12 or 16-Bit,1 to 10 MS/s, 4 Analog Inputs |
| 778218-000 | 制造商:TE Connectivity 功能描述:WALLBOX KIT LAN OUTLET WHITE |
| 77-82500 | 功能描述:D-Sub微型D連接器 50P R/A SOCKET HIGH/STD HOOD RoHS:否 制造商:3M Electronic Solutions Division 位置/觸點數(shù)量:26 排數(shù):2 安裝風格:SMD/SMT 安裝角:Right 端接類型:Solder 型式:Female |
發(fā)布緊急采購，3分鐘左右您將得到回復。