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參數(shù)資料
| 型號(hào)： | 7782 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory |
| 中文描述： | 32兆位（含2Mb × 16，雙行，突發(fā)）1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 13/63頁 |
| 文件大?。?/td> | 435K |
| 代理商： | 7782 |
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M58CR032C, M58CR032D
Protection Register, see Figure 6, for an example
of a single synchronous read operation.
Synchronous Burst Read.
The device also sup-
ports a synchronous burst read. In this mode a
burst sequence is started at the first clock edge
(rising or falling according to configuration set-
tings) after the falling edge of Latch Enable. After
a configurable delay of 2 to 5 clock cycles a new
data is output at each clock cycle. The burst se-
quence may be configured to be sequential or in-
terleaved and for a length of 4 or 8 words or for
continuous burst mode (see Table 5, Burst Type
Definition). Wrap and no-wrap modes are also
supported.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur. This delay
will depend on the starting address of the burst se-
quence; the worst case delay will occur when the
sequence is crossing a 64 word boundary and the
starting address was at the end of a four word
boundary. See the Burst Configuration Register
command for more details on all the possible set-
tings for the synchronous burst read (see Table 4).
It is possible to perform burst read across bank
boundaries (all banks in read array mode).
Table 3. Bus Operations
Note: 1. X = Don’t care.
2. T = transition, falling edge for L, rising or falling edge for K depending on M6 in the Burst Configuration Register. The burst sequence
is started on the first active clock edge after the falling edge of Latch Enable.
3. L can be tied to V
IH
if the valid address has been previously latched
Operation
E
G
W
L
K
RP
WP
DQ15-DQ0
Asynchronous Read
V
IL
V
IL
V
IH
V
IL(3)
X
V
IH
X
Data Output
Asynchronous Page Read
V
IL
V
IL
V
IH
V
IL(3)
X
V
IH
X
Data Output
Asynchronous Write
V
IL
V
IH
V
IL
V
IL(3)
X
V
IH
V
IH
Data Input
Output Disable
V
IL
V
IH
V
IH
X
X
V
IH
V
IH
Hi-Z
Standby
V
IH
X
X
X
X
V
IH
X
Hi-Z
Reset / Power-Down
X
X
X
X
X
V
IL
X
Hi-Z
Synchronous Read
V
IL
V
IL
V
IH
T
(2)
T
(2)
V
IH
X
Data Output
Synchronous Burst Read
V
IL
V
IL
V
IH
T
(2)
T
(2)
V
IH
X
Data Output
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