參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 71/97頁
文件大?。?/td> 1885K
代理商： 7640
70
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 1.84. DMAC Channel 0 Mode Register 2 (DMA0M2)
Fig. 1.85. DMAC Channel 1 Mode Register 2 (DMA1M2)
D0HRS3,2,1,0DMAC Channel 0 Hardware Transfer Request Source Bits (bits 3,2,1,0)
0000: Disable
0001: UART1 receive interrupt
0010: UART1 transmit interrupt
0011: TimerY interrupt
0100: External Interrupt 0
0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active)
0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active)
0111: USB EndPoint 3 IN_PKT_RDY signal (falling edge active)
1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active)
1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active)
1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active)
1011: USB EndPoint 3 OUT_PKT_RDY signal (rising edge active)
1100: MBI OBE
signal (rising edge active)
1101: MBI IBF
(data) signal (rising edge active)
1110: SIO receive/transmit interrupt
1111: CNTR1 interrupt
DOSWT
DMAC Channel 0 Software Transfer Trigger (bit 4)
0: No action (Bit is always read as “0”)
1: Writing “1” requests a channel 0 transfer
D0UMIE
DMAC Channel 0 USB and MBI Enable Bit (bit 5)
0: Disabled
1: Enabled
D0CRR
DMAC Channel 0 Transfer Initiation Source Capture Register Reset (bit 6)
0: No action (Bit is always read as “0”)
1: Setting to “1” causes reset of the channel 0 capture register
D0CEN
DMAC Channel 0 Enable Bit (bit 7)
0: Channel 0 disabled
1: Channel 0 enabled
D0CEN
D0UMIE
D0SWT
D0HRS3
D0HRS2
D0HRS1
D0HRS0
MSB
LSB
Address: 0041
16
Access: R/W
D0CRR
D1HRS3,2,1,0DMAC Channel 1 Hardware Transfer Request Source Bits (bits 3,2,1,0)
0000: Disable
0001: UART2 receive interrupt
0010: UART2 transmit interrupt
0011: TimerX interrupt
0100: External Interrupt 1
0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active)
0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active)
0111: USB EndPoint 4 IN_PKT_RDY signal (falling edge active)
1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active)
1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active)
1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active)
1011: USB EndPoint 4 OUT_PKT_RDY signal (rising edge active)
1100: MBI OBE
signal (rising edge active)
1101: MBI IBF
(data) signal (rising edge active)
1110: Timer interrupt
1111: CNTR0 interrupt
D1SWT
DMAC Channel 1 Software Transfer Trigger (bit 4)
0: No action (Bit is always read as “0”)
1: Writing “1” requests a channel 0 transfer
D1UMIE
DMAC Channel 1 USB and MBI Enable Bit (bit 5)
0: Disabled
1: Enabled
D1CRR
DMAC Channel 1 Transfer Initiation Source Capture Register Reset (bit 6)
0: No action (Bit is always read as “0”)
1: Setting to “1” causes reset of the channel 1 capture register
D1CEN
DMAC Channel 1 Enable Bit (bit 7)
0: Channel1 disabled
1: Channel 1 enabled
D1CEN
D1UMIE
D1SWT
D1HRS3
D1HRS2
D1HRS1
D1HRS0
MSB
7
LSB
0
Address: 0041
16
Access: R/W
Reset: 00
16
D1CRR
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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