參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 39/97頁
文件大?。?/td> 1885K
代理商： 7640
38
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.1 SIO Control Registers (SIOCON)
The Serial I/O Control Register 1 controls various SIO
functions such as transfer direction and transfer clock
divisor (see Figure 1.37). All of this register’s bits can
be read from and written to by software. At reset, this
register is cleared to 00
16
.
SIO Control Register 2 determines the transfer clock
phase and polarity, and also whether the SIO is to
function in SPI compatible mode (see Figure 1.38). All
of this register’s bits can be read from and written to
by software. At reset, this register is set to 18
16
.
Fig. 1.38. SIO Control Register 2 (SIOCON2)
Fig. 1.37. SIO Control Register 1 (SIOCON1)
ISCSel0-2
Internal Synchronization Clock Select Bit (bits 2,1,0)
Bit 2
Bit 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
SIO Port Selection Bit (bit 3)
0: I/O Port
1: TxD output, SCLK function
SRDY Output Select Bit (bit 4)
0: I/O Port
1: SRDY signal
Transfer Direction Select Bit (bit 5)
0: LSB first
1: MSB first
Synchronization Clock Select Bit (bit 6)
0: External Clock
1: Internal Clock
TxD Output Channel Bit (bit 7)
0: CMOS output
1: N-Channel open drain output
Bit 0
0: Internal Clock Divided by 2
1: Internal Clock Divided by 4
0: Internal Clock Divided by 8
1: Internal Clock Divided by 16
0: Internal Clock Divided by 32
1: Internal Clock Divided by 64
0: Internal Clock Divided by 128
1: Internal Clock Divided by 256
PSel
RDYSel
TDSel
SCSel
OCHCont
OCHCont
TDSel
RDYSel
PSel
ISCSel2 ISCSel1 ISCSel0
MSB
7
LSB
0
Address: 002B
16
Access: R/W
Reset: 40
16
SCSel
SPI
SPI Mode Selection Bit (bit 0)
0: Normal SIO mode
1: SPI compatibe mode
SIO Internal Clock Selection Bit (bit 1)
0:
1: SCSGCLK
SRXD Input Selection Bit (bit 2)
0: SRXD input disabled
1: SRXD input enabled
Clock Polarity Selection Bit (bit 3)
0: Clock is low between transfers
1: Clock is high between transfers
Clock Phase Selection Bit (bit 4)
0: Data is captured on the leading edge of serial clock, changes
on the following edge.
1: Data changes on the leading edge of serial clock, captured on
the following edge.
Reserved (Read/Write “0”)
CLKSEL
RXDSel
CPol
CPHa
Bit 5-7
Reserved
Reserved
CPha
CPol
RXDSel
CLKSEL
SP1
MSB
7
LSB
0
Address: 002C
16
Access: R/W
Reset: 18
16
Reserved
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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